Semiconductor memory with U-shaped channel
A semiconductor memory with a U-shaped channel comprises: a U-shaped channel region arranged in a semiconductor substrate, a source region, a drain region, a first layer of insulation film arranged on the U-shaped channel region, a floating gate provided with a notch, a second layer of insulation film, a control gate, a p-n junction diode arranged between the floating gate and the drain region, and a gate controlled diode formed by the control gate, the second layer of insulation film, and the p-n junction diode and using the control gate as a gate. Under the precondition of not increasing the manufacturing cost and difficulty of the semiconductor memory with a U-shaped channel and not affecting the performance of the semiconductor memory with a U-shaped channel, the dimension of a semiconductor storage device is further reduced and the chip density is increased by arranging the notch in the floating gate.
1. A U-shaped channel semiconductor memory, comprising:
a semiconductor substrate of a first doping type provided with a U-shaped channel region;
a source region and a drain region both of a second doping type provided in the semiconductor substrate, the U-shaped channel region being provided between the source region and the drain region;
a first layer of insulating film disposed on the U-shaped channel region, the first layer of insulating film extending to a horizontal surface of the drain region;
a floating gate opening region provided in the first layer of insulating film, the floating gate opening region being located on a side wall of the drain region on a top of the U-shaped channel region;
a floating gate of the first doping type covering the first layer of insulating film and the floating gate opening region; and
a p-n junction diode between the floating gate and the drain region;
wherein the U-shaped channel semiconductor memory further comprises:
a control gate covering the second layer of insulating film, the control gate, the second layer of insulating film, and the p-n junction diode forming a gated diode which uses the control gate as a gate; and
a notch of the floating gate provided between a top of the floating gate and the source region, the notch has a groove structure with asymmetrical position in the floating gate, wherein a side wall of the groove is in direct contact with the source region and an opposite side wall of the groove is in direct contact with the floating gate, a bottom of the control gate is formed in the groove, and a second layer of insulating film covering a side wall of the source region on the top of the U-shaped channel region and the floating gate, the second layer of insulating film extending towards both sides of the U-shaped channel region to the source region and the p-n junction diode.
2. The U-shaped channel semiconductor memory according to claim 1 , wherein the first doping type is n-type and the second doping type is p-type, a cathode of the gated diode is connected to the floating gate and an anode of the gated diode is connected to the drain region.
3. The U-shaped channel semiconductor memory according to claim 1 , wherein the first doping type is p-type and the second doping type is n-type, an anode of the gated diode is connected to the floating gate and a cathode of the gated diode is connected to the drain region.
4. The U-shaped channel semiconductor memory according to claim 1 , wherein a material of the first layer of insulating film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or an insulating material with a high dielectric constant, and the first layer of insulating film has a physical thickness of 1-20 nm.
5. The U-shaped channel semiconductor memory according to claim 1 , wherein a material of the second layer of insulating film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or an insulating material with a high dielectric constant, and the second layer of insulating film has a physical thickness of 1-20 nm.
6. The U-shaped channel semiconductor memory according to claim 1 , wherein a material of the floating gate is polycrystalline silicon.
7. The U-shaped channel semiconductor memory according to claim 1 , wherein a material of the control gate is metal, alloy, or doped polycrystalline silicon.
8. The U-shaped channel semiconductor memory according to claim 2 , wherein a material of the first layer of insulating film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or an insulating material with a high dielectric constant, and the first layer of insulating film is has a physical thickness of 1-20 nm.
9. The U-shaped channel semiconductor memory according to claim 3 , wherein a material of the first layer of insulating film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or an insulating material with a high dielectric constant, and the first layer of insulating film has a physical thickness of 1-20 nm.
10. The U-shaped channel semiconductor memory according to claim 2 , wherein a material of the second layer of insulating film is silicon dioxide, silicon nitride, silicon oxynitridc, hafnium oxide, or an insulating material with a high dielectric constant, and-the second layer of insulating film has a physical thickness of 1-20 nm.
11. The U-shaped channel semiconductor memory according to claim 3 , wherein a material of the second layer of insulating film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or an insulating material with a high dielectric constant, and-the second layer of insulating film has a physical thickness of 1-20 nm.
12. The U-shaped channel semiconductor memory according to claim 2 , wherein a material of the floating gate is polycrystalline silicon.
13. The U-shaped channel semiconductor memory according to claim 3 , wherein a material of the floating gate is polycrystalline silicon.
14. The U-shaped channel semiconductor memory according to claim 2 , wherein a material of the control gate is metal, alloy, or doped polycrystalline silicon.
15. The U-shaped channel semiconductor memory according to claim 3 , wherein a material of the control gate is metal, alloy, or doped polycrystalline silicon.