Nonvolatile memory cells, nonvolatile memory cell arrays including the same, and methods of fabricating the same

1. A nonvolatile memory device comprising:

a charge storage element having a MOS capacitor structure and including a control gate terminal connected to a word line and a body terminal connected to a body bias line;

a first half-MOS transistor having a first selection gate terminal connected to the word line and a first impurity junction terminal connected to a bit line and sharing the body terminal with the charge storage element; and

a second half-MOS transistor having a second selection gate terminal connected to the word line and a second impurity junction terminal connected to a source line and sharing the body terminal with the charge storage element,

wherein the charge storage element is coupled between the first and second half-MOS transistors so that the first half-MOS transistor, the charge storage element, and the second half-MOS transistor are connected in series.

2. The nonvolatile memory device of claim 1 , wherein the first impurity junction terminal is disposed at a first side of the charge storage element.

3. The nonvolatile memory device of claim 1 , wherein the second impurity junction terminal is disposed at a second side of the charge storage element.

4. The nonvolatile memory device of claim 1 , wherein each of the charge storage element, the first half-MOS transistor, and the second half-MOS transistor has an N-channel MOS structure.

5. A nonvolatile memory cell array including a plurality of unit cells arrayed in rows and columns in a matrix form, each of the plurality of unit cells comprising:

a charge storage element having a MOS capacitor structure including a control gate terminal connected to a word line and a body terminal connected to a body bias line;

a first half-MOS transistor having a first selection gate terminal connected to the word line and a first impurity junction terminal connected to a bit line and sharing the body terminal with the charge storage element; and

a second half-MOS transistor having a second selection gate terminal connected to the word line and a second impurity junction terminal connected to a source line and sharing the body terminal with the charge storage element,

wherein the charge storage element is coupled between the first and second half-MOS transistors so that the first half-MOS transistor, the charge storage element and the second half-MOS transistor are connected in series.

6. The nonvolatile memory cell array of claim 5 ,

wherein the word line is any one of a plurality of word lines disposed in the rows, respectively,

wherein the body bias line is any one of a plurality of body bias lines disposed in the columns, respectively, and

wherein the unit cells disposed in each row share one of the plurality of word lines with each other.

7. The nonvolatile memory cell array of claim 5 ,

wherein the bit line is any one of a plurality of bit lines disposed in the columns, respectively,

wherein the body bias line is any one of a plurality of body bias lines disposed in the columns, respectively, and

wherein the unit cells disposed in each column share one of the plurality of bit lines and one of the plurality of body bias lines with each other.

8. The nonvolatile memory cell array of claim 5 , wherein the plurality of unit cells share the source line with each other.

9. The nonvolatile memory cell array of claim 5 ,

wherein the second impurity junction terminals of unit cells arrayed in an N th row are connected to the second impurity junction terminals of unit cells arrayed in an (N+1) th row, respectively, wherein the first impurity junction terminals of the unit cells arrayed in the N th row are connected to the first impurity junction terminals of the unit cell arrayed in an (N−1) th row of, respectively, and

wherein N is an integer.