Power amplification circuit

1. A power amplification circuit comprising:

a first amplification transistor, wherein a first signal is input to a base or gate of the first amplification transistor and a second signal obtained by amplifying the first signal is output from a collector or drain of the first amplification transistor; and

a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor;

wherein the first bias circuit includes

a first transistor, wherein a power supply voltage is supplied to a collector or drain of the first transistor, a first prescribed voltage is supplied to a base or gate of the first transistor, and the first bias current is output from an emitter or source of the first transistor, and

a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground,

wherein the first control circuit includes

a first resistor and a first switch connected in series with each other, and

wherein the first switch is on when the power amplification circuit is in a high power mode and is off when the power amplification circuit is in a low power mode, the first switch being controlled in accordance with a control signal that represents a power mode.

2. The power amplification circuit according to claim 1 ,

wherein the first bias circuit further includes

a second transistor, wherein the power supply voltage is supplied to a collector or drain of the second transistor and a second bias current is output from an emitter or source of the second transistor to the base or gate of the first amplification transistor, and

a second control circuit that controls the second transistor to be on when the power amplification circuit is in the high power mode and controls the second transistor to be off when the power amplification circuit is in the low power mode in accordance with the control signal.

3. The power amplification circuit according to claim 2 , wherein the second control circuit comprises a switch connected between a base or gate of the second transistor and the base or gate of the first transistor.

4. The power amplification circuit according to claim 3 , wherein the switch is controlled to supply the first prescribed voltage to the base or gate of the second transistor and to the base or gate of the first transistor, in accordance with the control signal.

5. The power amplification circuit according to claim 1 ,

wherein the first bias circuit further includes

a third control circuit that controls a resistance between the base or gate of the first amplification transistor and the emitter or source of the first transistor in accordance with a bias control signal supplied from outside of the first bias circuit.

6. The power amplification circuit according to claim 5 ,

wherein the third control circuit includes a second resistor and a second switch provided between the base or gate of the first amplification transistor and the emitter or source of the first transistor,

the second resistor and the second switch are connected in series with each other, and

the second switch is controlled in accordance with the bias control signal.

7. The power amplification circuit according to claim 1 , further comprising:

a second amplification transistor, wherein a third signal is input to a base or gate of the second amplification transistor, and the first signal, which is obtained by amplifying the third signal, is output from a collector or a drain of the second amplification transistor; and

a second bias circuit that supplies a third bias current to a base or gate of the second amplification transistor;

wherein the second bias circuit includes

a third transistor, wherein the power supply voltage is supplied to a collector or drain of the third transistor, a second prescribed voltage is supplied to a base or gate of the third transistor, and the third bias current is output from an emitter or source of the third transistor, and

a fourth control circuit that controls an electrical connection between the emitter or source of the third transistor and ground,

wherein the fourth control circuit includes a third resistor and a third switch connected in series with each other, and

wherein the third switch is on when the power amplification circuit is in the high power mode and is off when the power amplification circuit is in the low power mode, the third switch being controlled in accordance with the control signal.

8. The power amplification circuit according to claim 7 , wherein the second amplification transistor and the second bias circuit are part of a first amplification stage, and the first amplification transistor and the first bias circuit are part of a second amplification stage.

9. The power amplification circuit according to claim 1 , further comprising a third amplification transistor, wherein the first amplification transistor and the third amplification transistor form parallel amplification paths for the first signal.

10. The power amplification circuit according to claim 9 , wherein the first signal is input to a base or gate of the third amplification transistor and the second signal obtained by amplifying the first signal is output from a collector or drain of the third amplification transistor.

11. The power amplification circuit according to claim 10 , wherein the first bias circuit supplies a fourth bias current to the base or gate of the third amplification transistor.

12. The power amplification circuit according to claim 11 , further comprising a fourth resistor and a fourth switch connected in series between the emitter or source of the first transistor and the base or gate of the third amplification transistor, the fourth switch being controlled in accordance with the control signal.

13. The power amplification circuit according to claim 9 , further comprising:

a second amplification transistor, wherein a third signal is input to a base or gate of the second amplification transistor, and the first signal, which is obtained by amplifying the third signal, is output from a collector or a drain of the second amplification transistor; and

a second bias circuit that supplies a third bias current to a base or gate of the second amplification transistor;

wherein the second bias circuit includes

a third transistor, wherein the power supply voltage is supplied to a collector or drain of the third transistor, a second prescribed voltage is supplied to a base or gate of the third transistor, and the third bias current is output from an emitter or source of the third transistor, and

a fourth control circuit that controls an electrical connection between the emitter or source of the third transistor and ground,

wherein the fourth control circuit includes a third resistor and a third switch connected in series with each other, and

wherein the third switch is on when the power amplification circuit is in the high power mode and is off when the power amplification circuit is in the low power mode, the third switch being controlled in accordance with the control signal.

14. The power amplification circuit according to claim 10 , further comprising:

a second amplification transistor, wherein a third signal is input to a base or gate of the second amplification transistor, and the first signal, which is obtained by amplifying the third signal, is output from a collector or a drain of the second amplification transistor; and

a second bias circuit that supplies a third bias current to a base or gate of the second amplification transistor;

wherein the second bias circuit includes

a third transistor, wherein the power supply voltage is supplied to a collector or drain of the third transistor, a second prescribed voltage is supplied to a base or gate of the third transistor, and the third bias current is output from an emitter or source of the third transistor, and

a fourth control circuit that controls an electrical connection between the emitter or source of the third transistor and ground,

wherein the fourth control circuit includes a third resistor and a third switch connected in series with each other, and

wherein the third switch is on when the power amplification circuit is in the high power mode and is off when the power amplification circuit is in the low power mode, the third switch being controlled in accordance with the control signal.

15. The power amplification circuit according to claim 11 , further comprising:

a second amplification transistor, wherein a third signal is input to a base or gate of the second amplification transistor, and the first signal, which is obtained by amplifying the third signal, is output from a collector or a drain of the second amplification transistor; and

a second bias circuit that supplies a third bias current to a base or gate of the second amplification transistor;

wherein the second bias circuit includes

a third transistor, wherein the power supply voltage is supplied to a collector or drain of the third transistor, a second prescribed voltage is supplied to a base or gate of the third transistor, and the third bias current is output from an emitter or source of the third transistor, and

a fourth control circuit that controls an electrical connection between the emitter or source of the third transistor and ground,

wherein the fourth control circuit includes a third resistor and a third switch connected in series with each other, and

wherein the third switch is on when the power amplification circuit is in the high power mode and is off when the power amplification circuit is in the low power mode, the third switch being controlled in accordance with the control signal.

16. The power amplification circuit according to claim 12 , further comprising:

a second amplification transistor, wherein a third signal is input to a base or gate of the second amplification transistor, and the first signal, which is obtained by amplifying the third signal, is output from a collector or a drain of the second amplification transistor; and

a second bias circuit that supplies a third bias current to a base or gate of the second amplification transistor;

wherein the second bias circuit includes

a third transistor, wherein the power supply voltage is supplied to a collector or drain of the third transistor, a second prescribed voltage is supplied to a base or gate of the third transistor, and the third bias current is output from an emitter or source of the third transistor, and

a fourth control circuit that controls an electrical connection between the emitter or source of the third transistor and ground,

wherein the fourth control circuit includes a third resistor and a third switch connected in series with each other, and

wherein the third switch is on when the power amplification circuit is in the high power mode and is off when the power amplification circuit is in the low power mode, the third switch being controlled in accordance with the control signal.