Extended-height DIMM
An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer, or a register control device and data buffers, which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits.
1. An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for a DIMM and a maximum number of devices allowed to reside on a DIMM, the extended-height DIMM comprising:
a printed circuit board (PCB) having an edge connector designed to mate with a respective one of the slots, a height of said PCB being greater than said maximum height;
a plurality of memory devices on said PCB which exceeds said maximum number of devices;
a register control device (RCD) and data buffer (DB) devices on said PCB and arranged to operate as an interface between a host controller's data and command/address busses and all of the plurality of memory devices;
such that said extended-height DIMM provides greater memory capacity than would a DIMM which complies with said maximum height and said maximum number of devices in the JEDEC standard.
2. The extended-height DIMM of claim 1 , wherein said maximum height is approximately 31 mm and said PCB has a height of approximately 56 mm.
3. The extended-height DIMM of claim 1 , wherein said maximum number of devices is 36 and said PCB can accommodate as many as 72 devices.
4. The extended-height DIMM of claim 1 , wherein said memory devices of the plurality of memory devices are planar DDR4 ×4 DRAMs.
5. The extended-height DIMM of claim 4 , wherein a greater number of planar DDR4 ×4 DRAMs than the maximum number of devices accommodated by said extended-height DIMM enable said extended-height DIMM to provide a memory capacity comparable to that of a DIMM on which stacked DRAMs reside and which is in compliance with said JEDEC standard.
6. The extended-height DIMM of claim 1 , wherein said memory devices of the plurality of memory devices are stacked DRAMs.
7. The extended-height DIMM of claim 1 , wherein said slots are designed to receive DIMMs in compliance with the DDR4 UDIMMs, RDIMMs and LRDIMMs JEDEC standards.
8. The extended-height DIMM of claim 1 , wherein said one of the DB devices is a JEDEC-compatible memory buffer.
9. The extended-height DIMM of claim 1 , wherein said extended-height DIMM is arranged to support up to 4 physical ranks.
10. The extended-height DIMM of claim 1 , wherein said extended-height DIMM is arranged to operate at up to DDR4 3200 speed.
11. The extended-height DIMM of claim 1 , wherein said extended-height DIMM comprises one RCD and 9 DB devices.
12. The extended-height DIMM of claim 1 , wherein said RCD is arranged to buffer clock and command and address signals from a host controller, and to issue commands to said DB devices.
13. The extended-height DIMM of claim 1 , wherein said memory devices of the plurality of memory devices are DRAMs, wherein said DB devices are arranged to retime data signals from a host controller to the DRAMs.
14. The extended-height DIMM of claim 1 , wherein said memory devices of the plurality of memory devices are DRAMs, and wherein each of said DB devices comprises 2 sets of 4 bi-directional data signal (DQ) lines and said DB devices are arranged to buffer data between a host controller and the DRAMs.
15. The extended-height DIMM of claim 14 , wherein each of said DB devices is arranged to communicate with two DRAMs.