IP Library Granted Patent US 9,747,080
Granted Patent B2
US 9,747,080 · App. 15/062,761 · Granted Aug 29, 2017

Software design sharing systems and methods

Inventor: Kevin D. Howard (Tempe, AZ)
Assignee: Massively Parallel Technologies, Inc.
G06F8/20G06F8/30G06F8/36
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Quick Facts
Patent No.
US 9,747,080
App. No.
15/062,761
Granted
Aug 29, 2017
Kind
B2
Abstract

A system, method and software product shares a software design. A design sharer having machine readable instructions stored within memory of a development server and executable by a processor of the development server interacts with a first user to select a first portion of a first hierarchical software design. The design sharer saves the first portion within a public workspace. The design sharer interacts with a second user having access to the public workspace to select the first portion and inserts the first portion into a second hierarchical software design.

Claims (21)

1. A method for implementing a hierarchical software design formed of a plurality of decomposition levels each comprising a control, at least one process, wherein each decomposable process has a corresponding sub-graph, and where each non-decomposable processes has associated code that implements functionality of the process, comprising:

translating one of the decomposition levels directly into an executable finite state machine having:

a plurality of states including one state corresponding to the control and additional states each respectively corresponding to one of the non-decomposable processes and formed of executable code associated with the non-decomposable process; and

state transitions formed of interpreted code that represents control flow between the control state and the additional states defined within sub-graphs of the decomposable processes; and

interpreting the state transitions to invoke execution of the states to implement the hierarchical software design.

2. The method of claim 1 , further comprising translating the executable finite state machine into an optimized executable finite state machine by altering the state transitions such that one of the additional states directly invokes another of the additional states.

3. The method of claim 2 , the step of translating the executable finite state machine into an optimized executable finite state machine further comprising removing the control state when the decomposition level includes associated processes without a looping condition.

4. The method of claim 2 , the step of translating the executable finite state machine into an optimized executable finite state machine further comprising inserting a looping state transition between one of the additional states and the control state, and a looping end state transition from the control state when the decomposition levels includes a loop across associated processes therein.

5. The method of claim 2 , the step of translating the executable finite state machine into an optimized executable finite state machine further comprising inserting (a) a first conditional state transition between a first one of the additional states and the control state, and (b) a second conditional state transition between a second of the additional states and the control state when the decomposition levels includes multiple unassociated non-decomposable processes.

6. The method of claim 1 , further comprising:

merging two of the non-decomposable processes to form one of the states based upon a merge indicator for each of the two processes within the hierarchical software design;

generating, within the one of the states, conditional statements and flags based upon control flow for the two processes; and

compiling the conditional statements and flags with code of the two processes to form the one of the states.

7. The method of claim 6 , wherein after the step of merging, the functionality details of the individual merged processes is hidden.

8. The method of claim 6 , wherein after the step of merging, a processing time of processing the hierarchical software design is reduced.

9. A method for implementing a hierarchical software design formed of a plurality of decomposition levels each comprising a control, at least one process, wherein each decomposable process has a corresponding sub-graph, and where each non-decomposable processes has associated code that implements functionality of the process, comprising:

merging two of the non-decomposable processes to form one of the states based upon a merge indicator for each of the two processes within the hierarchical software design;

generating, within the one of the states, conditional statements and flags based upon control flow for the two processes; and

compiling the conditional statements and flags with code of the two processes to form the one of the states.

10. The method of claim 9 , wherein after the step of merging, the functionality details of the individual merged processes is hidden within the hierarchical software design.

11. The method of claim 9 , wherein after the step of merging, a processing time of processing the hierarchical software design is reduced.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2024
From: SAFEGUARD BIOSYSTEMS HOLDING LIMITED
To: SAFEGUARD DX LIMITED
Reel/Frame 069088/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2016
From: HOWARD, KEVIN D.
To: MASSIVELY PARALLEL TECHNOLOGIES, INC.
Reel/Frame 037911/0719 →
Continuity (3)
Continuation In Part 14306161 · Jun 16, 2014
Provisional Application 61835254 · Jun 14, 2013
Related Publication 20160188300A1 · Jun 30, 2016