IP Library Granted Patent US 9,748,256
Granted Patent B2
US 9,748,256 · App. 14/924,525 · Granted Aug 29, 2017

Semiconductor device and method of forming the same

Inventors: Wei-Chang Liu (Singapore, SG); Zhen Chen (Singapore, SG); Shen-De Wang (Hsinchu County, TW); Wang Xiang (Singapore, SG); Yi-Shan Chiu (Taoyuan, TW); Wei Ta (Singapore, SG)
Assignee: United Microelectronics Corp.
H01L27/11524H01L21/28273
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Quick Facts
Patent No.
US 9,748,256
App. No.
14/924,525
Granted
Aug 29, 2017
Kind
B2
Abstract

Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

Claims (13)

1. A semiconductor device, comprising:

a memory gate structure; and

a select gate structure, closely adjacent to the memory gate structure, wherein an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure,

wherein the select gate structure has a flat top surface and an outer side surface away from the memory gate structure, and a portion of the outer side surface adjacent to the flat top surface is inclined, the memory gate structure has a flat top surface lower than the flat top surface of the select gate structure and a top surface of the air gap is lower than the flat top surface of the select gate structure;

wherein the insulating layer simultaneously covers the flat top surfaces and outer side surface of the select gate structure and the memory gate structure;

wherein the memory gate structure has a L-shaped spacer;

wherein the air gap is sandwiched between the L-shaped spacer and the select gate structure;

wherein the air gap is directly contacting the spacer;

wherein the air gap has a width ranging from 10 angstroms to 20 angstroms; and

wherein the air gap is under a vacuum condition.

2. The semiconductor device of claim 1 , wherein the insulating layer comprises silicon oxide.

3. The semiconductor device of claim 1 , further comprising a doped region disposed in a substrate below the air gap.

4. The semiconductor device of claim 1 , wherein the memory gate structure comprises a charge storage layer and a gate sequentially disposed on a substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2015
From: LIU, WEI-CHANG; CHEN, ZHEN; WANG, SHEN-DE; XIANG, WANG; CHIU, YI-SHAN; TA, WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036896/0361 →
Priority Claims (1)
TW 104130582 A · Sep 16, 2015 · national
Continuity (1)
Related Publication 20170077110A1 · Mar 16, 2017