Reduced thermal transfer to Peltier cooled FETs
A printed circuit board for use with a cooling device configured to cool at least one device is provided. The printed circuit board includes a substrate having a first surface and a second surface opposing the first surface; a ground plane on the first surface of the substrate, and circuitry in a circuit-region on the second surface of the substrate. The ground plane includes a patterned-region that is patterned with an array of holes. The circuitry is configured for use with the at least one device to be cooled. When a first side of the cooling device contacts the ground plane, and when the at least one device to be cooled contacts the circuitry, a reduced cross-sectional area of the patterned-region prevents heat from a second side of the cooling device from degrading performance of the at least one device.
1. A printed circuit board (PCB) for use with a cooling device configured to cool at least one device, the at least one device being at least one of an electronic device, an optical device, an electro-optic device, and a magnetic device, the PCB comprising:
a substrate having a first surface and a second surface opposing the first surface;
a ground plane on the first surface of the substrate, the ground plane including a patterned-region that is patterned with an array of holes with some desired ratio of metal to gap; and
circuitry in a circuit-region on the second surface of the substrate, the circuitry configured for use with the at least one device to be cooled,
wherein, when a first side of the cooling device contacts the ground plane, and when the at least one device to be cooled contacts the circuitry, a reduced cross-sectional area of the patterned-region in the ground plane increases the thermal resistance of the patterned-region reducing thermal transfer, thereby reducing degradation of a performance of the at least one device.
2. The printed circuit board of claim 1 , wherein the ground plane further includes at least one solid-region surrounding the patterned-region.
3. The printed circuit board of claim 2 , wherein the at least one solid-region includes:
a first-solid-region surrounding an outer perimeter of the patterned-region; and
a second-solid-region surrounded by an inner perimeter of the patterned-region.
4. The printed circuit board of claim 3 , wherein the first side of the cooling device is a cool side, the second side of the cooling device is a hot side, wherein when the printed circuit board is operably positioned on a thermally conductive structure, wherein heat generated at the hot side of the cooling device is thermally conducted to the first-solid-region of the ground plane, and wherein the reduced cross-sectional area of the patterned-region mitigates the flow of heat to: the device to be cooled, and the cool side of the cooling device.
5. The printed circuit board of claim 3 , further comprising:
a ground connection electrically connecting the circuitry to the second-solid-region of the ground plane through the substrate.
6. The printed circuit board of claim 2 , wherein the at least one solid-region surrounding the patterned-region is a single solid-region, the printed circuit board further comprising:
a ground connection electrically connecting the circuitry to the patterned-region of the ground plane through the substrate.
7. The printed circuit board of claim 6 , wherein the first side of the cooling device is a cool side, the second side of the cooling device is a hot side, wherein when the printed circuit board is operably positioned on a thermally conductive structure, heat generated at the hot side of the cooling device is thermally conducted to the at least one solid-region of the ground plane, and wherein the reduced cross-sectional area of the patterned-region mitigates the flow of heat to: the device to be cooled, and the cool side of the cooling device.
8. The printed circuit board of claim 1 , wherein the at least one device is a field effect transistor (FET) in a low noise amplifier, wherein the circuitry includes a source microstrip, and a drain microstrip, and wherein a pitch of the array of holes patterned in the patterned-region of ground plane is less than a quarter of wavelength of the electromagnetic wave propagating in the source microstrip and the drain microstrip.
9. The printed circuit board of claim 8 , wherein the cooling device is a Peltier device thermoelectrically cooling the field effect transistor (FET) in a thermally conductive structure.
10. The printed circuit board of claim 8 , wherein the circuitry in the circuit-region on the second surface of the substrate includes a circuitry-patterned-region that is patterned with an array of holes.