Methods for manufacturing and operating a memory device and a method for operating a system having the same

1. A method for manufacturing a memory device, comprising:

detecting, with a tester, whether memory cells included in a memory device are defective; and

programming, with the tester, start addresses of defect-free memory regions for addressing modes in the memory device based on a result of the detection,

wherein the start addresses are different from each other according to a size of a corresponding one of the defect-free memory regions.

2. The method of claim 1 , wherein, when the memory device is a dynamic random-access memory (DRAM) including banks, each of the banks includes memory cells, and each of the defect-free memory regions is included in at least one of the banks.

3. The method of claim 1 , wherein the start addresses are stored in a mode register.

4. The method of claim 1 , wherein the start addresses are stored using fuses.

5. The method of claim 1 , wherein when the memory device includes a first memory and a second memory, the first memory includes the defect-free memory regions and the second memory stores the start addresses.

6. The method of claim 5 , wherein the first memory is a dual data rate (DDR) memory, and the second memory is a flash memory, a dynamic random-access memory (DRAM) including the flash memory, a phase-change random-access memory (PRAM), a magnetoresistive random-access memory (MRAM), a resistive random-access memory (RRAM), an embedded multimedia card (eMMC), a solid state drive (SSD), a universal serial bus (USB) flash drive, or a universal flash storage (UFS).

7. A method for operating a memory device, comprising:

receiving an instruction from a host; and

transferring at least one of start addresses of defect-free memory regions for addressing modes to the host in response to the instruction,

wherein the start addresses of defect-free memory regions are programmed in the memory device in a mass-production phase, wherein the start addresses are different from each other according to a size of a corresponding one of the defect-free memory regions.

8. The method of claim 7 , wherein the memory device is a dual data rate (DDR) memory, and the start addresses are stored in a mode register.

9. The method of claim 7 , wherein the memory device includes:

a dynamic random-access memory (DRAM) which includes the defect-free memory regions;

a non-volatile memory which stores the start addresses; and

a DRAM interface which reads at least one of the start addresses stored in the non-volatile memory in response to the instruction, and transfers the at least one read start address to the host.

10. A method for operating a memory system which includes a host, a first memory device, and a second memory device, comprising:

reading, by the host, a first start address of a plurality of start addresses from the first memory device, wherein the plurality of start addresses correspond to defect-free memory regions for addressing modes;

reading, by the host, a boot loader from the second memory device; and

writing, by the host, the boot loader in a defect-free memory region corresponding to the first start address,

wherein the addressing modes include a row-bank-column addressing mode and a bank-row-column addressing mode.

11. The method of claim 10 , wherein the first memory device is a dual data rate (DDR) memory, and the start addresses are stored in a mode register.

12. The method of claim 10 , wherein the first memory device includes:

a dynamic random-access memory (DRAM) which includes the defect-free memory region;

a non-volatile memory which stores the start addresses; and

a DRAM interface which reads the first start address stored in the non-volatile memory in response to an instruction output from the host, and transfers the first start address to the host.

13. The method of claim 10 , wherein the start addresses are different from each other according to a size of a corresponding one of the defect-free memory regions.

14. The method of claim 10 , wherein the host includes:

a central processing unit (CPU);

a first memory controller which reads the first start addresses according to a control of the CPU; and

a second memory controller which reads the boot loader according to a control of the CPU,

wherein the first memory controller writes the boot loader in the defect-free memory region corresponding to the first start address.

15. The method of claim 10 , wherein the host includes:

a central processing unit (CPU);

a first memory controller which reads the first start addresses when the system is booted; and

a second memory controller which reads the boot loader according to a control of the CPU,

wherein the first memory controller writes the boot loader in the defect-free memory region corresponding to the first start address.

16. The method of claim 7 , wherein each start address is determined by a row value, a bank value, and a column value.