3D integration using Al—Ge eutectic bond interconnect
Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.
1. An apparatus comprising:
a first CMOS wafer;
a second CMOS wafer including a depression within a surface of the second CMOS wafer, wherein the depression includes an aluminum surface; and
a eutectic bond connecting the first CMOS wafer to the second CMOS wafer, wherein
the eutectic bond includes aluminum and germanium,
the eutectic bond has a melting point which is lower than the melting point of aluminum and the melting point of germanium, and
the eutectic bond includes the aluminum surface.
2. The apparatus of claim 1 , wherein
the first CMOS wafer includes an aluminum standoff and a germanium layer on the first standoff, and
the eutectic bond includes the aluminum standoff.
3. The apparatus of claim 1 , wherein
the first CMOS wafer includes a germanium standoff, and
the eutectic bond includes the germanium standoff.
4. The apparatus of claim 1 , further comprising a plurality of eutectic bonds connecting the first CMOS wafer to the second CMOS wafer.
5. The apparatus of claim 1 , further comprising a standoff height between the first CMOS wafer and the second CMOS wafer, wherein the standoff height is between 0 and 2000 Å.
6. An apparatus comprising:
a first feature on a first CMOS wafer, wherein the first feature is a standoff with a height;
a second feature on a second CMOS wafer, wherein the second feature is a depression with a depth, wherein the height is greater than the depth; and
a eutectic bond connecting the first feature to the second feature, wherein the eutectic bond has a melting point which is lower than the melting point of the first feature and the melting point of the second feature.
7. The apparatus of claim 6 , wherein the first feature includes aluminum.
8. The apparatus of claim 6 , wherein the second feature includes germanium.
9. The apparatus of claim 6 , wherein the eutectic bond includes portions of the first feature and portions of the second feature melted together.
10. The apparatus of claim 6 , wherein the first feature includes a height less than 500 Å.
11. An apparatus comprising:
a first CMOS wafer;
a second CMOS wafer including a depression within a surface of the second CMOS wafer, wherein the depression includes a germanium surface; and
a eutectic bond connecting the first CMOS wafer to the second CMOS wafer, wherein
the eutectic bond includes aluminum and germanium,
the eutectic bond includes a melting point which is lower than the melting point of aluminum and the melting point of germanium; and
the eutectic bond includes the germanium surface.
12. The apparatus of claim 11 , further comprising a plurality of eutectic bonds connecting the first CMOS wafer to the second CMOS wafer.
13. The apparatus of claim 11 , further comprising a standoff height between the first CMOS wafer and the second CMOS wafer, wherein the standoff height is between 0 and 2000 Å.
14. An apparatus comprising:
a first feature on a first CMOS wafer;
a second feature on a second CMOS wafer; and
a eutectic bond connecting the first feature to the second feature, wherein
the eutectic bond includes a melting point which is lower than the melting point of the first feature and the melting point of the second feature, and
a width of the eutectic bond is narrower than a width of the second feature.
15. The apparatus of claim 14 , wherein the first feature includes aluminum.
16. The apparatus of claim 14 , wherein the second feature includes germanium.
17. The apparatus of claim 14 , wherein the eutectic bond includes portions of the first feature and portions of the second feature melted together.
18. The apparatus of claim 14 , wherein the first feature includes a height less than 500 Å.