ESD protection device with improved bipolar gain using cutout in the body well
An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.
1. An integrated circuit, comprising:
a substrate comprising a p-type semiconductor;
a symmetric p-channel metal oxide semiconductor (PMOS) transistor disposed in said substrate;
a p-type n-channel metal oxide semiconductor (NMOS) body well disposed in said substrate;
a symmetric NMOS transistor disposed in said p-type NMOS body well; and
an NMOS silicon controlled rectifier (SCR), including:
a p-type body well disposed in said substrate, said p-type body well having a cutout with a lower doping density;
an n-type source region disposed in said p-type body well over said cutout;
an n-type region disposed in said substrate under said cutout, said n-type region being connected to an n-type drain region; and
a p-type body contact region, disposed in said p-type body well over said cutout;
wherein said NMOS SCR is a drain extended NMOS SCR, and wherein:
said p-type body well is a p-type drain extended body well;
a deep n-type well is disposed in said substrate, extending laterally to abut said p-type drain extended body well, so that said deep n-type well provides an extended drain of said drain extended transistor; and
a p-type SCR contact region is disposed in said deep n-type well.
2. The integrated circuit of claim 1 , in which said n-type region disposed under said cutout is an n-type buried layer; so that said deep n-type well contacts a top of said n-type buried layer.
3. An integrated circuit, comprising:
a substrate comprising a p-type semiconductor;
a symmetric p-channel metal oxide semiconductor (PMOS) transistor disposed in said substrate;
a p-type n-channel metal oxide semiconductor (NMOS) body well disposed in said substrate;
a symmetric NMOS transistor disposed in said p-type NMOS body well; and
an NMOS silicon controlled rectifier (SCR), including:
a p-type body well disposed in said substrate, said p-type body well having a cutout with a lower doping density;
an n-type source region disposed in said p-type body well over said cutout;
an n-type region disposed in said substrate under said cutout, said n-type region being connected to an n-type drain region; and
a p-type body contact region, disposed in said p-type body well over said cutout, in which said NMOS SCR is a symmetric NMOS SCR, wherein:
said p-type body well is an isolated p-type body well;
a deep n-type well is disposed in said substrate, electrically isolating said isolated p-type body well from said substrate; and
a p-type SCR contact region is disposed in said deep n-type well.