IP Library › Granted Patent US 9,755,064
Granted Patent B2
US 9,755,064 · App. 15/048,112 · Granted Sep 5, 2017

Semiconductor device and method for manufacturing the same

Inventors: Teruyuki Ohashi (Kawasaki, JP); Yuichiro Mitani (Miura, JP); Tatsuo Shimizu (Shinagawa, JP); Ryosuke Iijima (Setagaya, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/7802H01L21/049H01L21/3003H01L29/045H01L29/1095H01L29/1608H01L29/66068
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Quick Facts
Patent No.
US 9,755,064
App. No.
15/048,112
Granted
Sep 5, 2017
Kind
B2
Abstract

A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×10 20 cm −3 or more and a maximum concentration of hydrogen (H) in the region being 1×10 19 cm −3 or less.

Claims (27)

1. A semiconductor device comprising:

a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface, having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction;

a gate electrode;

a gate insulating layer provided between the surface and the gate electrode; and

a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×10 20 cm −3 or more and a maximum concentration of hydrogen (H) in the region being 1×10 19 cm −3 or less.

2. The device according to claim 1 , wherein concentration distribution of deuterium in the region has a peak, and a full width at half maximum of the peak is 10 nm or less.

3. The device according to claim 1 , wherein the maximum concentration of deuterium in the region is 1×10 21 cm −3 or more.

4. The device according to claim 1 , wherein the gate insulating layer is a silicon oxide film.

5. A method for manufacturing a semiconductor device comprising:

forming a gate insulating layer on a surface of a SiC layer, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face, or, the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction;

performing first heat treatment in an atmosphere containing deuterium after forming the gate insulating layer; and

forming a gate electrode on the gate insulating layer after performing the first heat treatment.

6. The method according to claim 5 , wherein the gate insulating layer is a silicon oxide film.

7. The method according to claim 5 , further comprising performing second heat treatment of 800° C. or more after the first heat treatment.

8. The method according to claim 5 , wherein the gate insulating layer is a deposition film.

9. The method according to claim 5 , wherein the gate insulating layer is a thermal oxide film.

10. The method according to claim 5 , wherein the first heat treatment is performed at 900° C.

11. A method for manufacturing a semiconductor device comprising:

forming a gate insulating layer on a surface of a SiC layer, the forming the gate insulating layer including thermally-oxidizing the surface in an atmosphere containing deuterium and oxygen, the surface inclined at an angle of 0° to 10° with respect to a {000-1}face, or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction; and

forming a gate electrode on the gate insulating layer.

12. The method according to claim 11 , wherein the gate insulating layer is formed by depositing an insulating film after the thermally-oxidizing the surface.

13. The method according to claim 12 , wherein the insulating film is a silicon oxide film.

14. The method according to claim 11 , further comprising performing a heat treatment of 800° C. or more after the forming the gate insulating layer.

15. The method according to claim 11 , wherein the thermally-oxidizing the surface is performed at 800° C. or more.

16. The method according to claim 11 , comprising bonding deuterium (D) in the region to carbon at the surface.

17. The device according to claim 1 , wherein deuterium (D) in the region is bonded to carbon at the surface.

18. The method according to claim 5 , comprising bonding deuterium (D) in the region to carbon at the surface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2016
From: OHASHI, TERUYUKI; MITANI, YUICHIRO; SHIMIZU, TATSUO; IIJIMA, RYOSUKE
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038245/0288 →
Priority Claims (1)
JP 2015-033595 · Feb 24, 2015 · national
Continuity (1)
Related Publication 20160247907A1 · Aug 25, 2016