Semiconductor device including a multi-channel active pattern

1. A semiconductor device, comprising:

a multi-channel active pattern;

a field insulation layer disposed on the multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the multi-channel active pattern;

a gate electrode crossing the multi-channel active pattern, the gate electrode being disposed on the field insulation layer;

a source or drain disposed between the gate electrode and the first region of the field insulation layer and including a facet that is a slanted sidewall, the facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the multi-channel active pattern; and

a dummy gate electrode disposed on the first region of the field insulation layer.

2. The semiconductor device of claim 1 , wherein the source or drain contacts the first region of the field insulation layer.

3. The semiconductor device of claim 2 , wherein the facet contacts a sidewall of the first region of the field insulation layer.

4. The semiconductor device of claim 1 , wherein a top surface of the gate electrode is coplanar with a top surface of the dummy gate electrode.

5. The semiconductor device of claim 1 , further comprising a spacer disposed on a sidewall of the dummy gate electrode, wherein at least a portion of a bottom surface of the spacer overlaps with the source or drain.

6. The semiconductor device of claim 5 , further comprising an insulation pattern interposed between the spacer and a region of the source or drain overlapping with the spacer.

7. A semiconductor device, comprising:

a first multi-channel active pattern;

afield insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern;

a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer;

a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet that is a slanted sidewall, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern;

a second multi-channel active pattern parallel with the first multi-channel active pattern, the first region of the field insulation layer being interposed between the first multi-channel active pattern and the second multi-channel active pattern;

a second gate electrode crossing the second multi-channel active pattern, the second gate electrode being disposed on the field insulation layer; and

a second source or drain disposed between the second gate electrode and the first region of the field insulation layer,

wherein the second source or drain includes a second facet disposed adjacent to the sidewall of the first region of the field insulation layer.

8. The semiconductor device of claim 7 , further comprising:

a dummy gate electrode disposed on the first region of the field insulation layer; and

a spacer disposed on a sidewall of the dummy gate electrode, wherein a bottom surface of the spacer overlaps with the first source or drain and the second source or drain.

9. A semiconductor device, comprising:

a multi-channel active pattern;

a field insulation layer disposed on at least two sides of the multi-channel active pattern and including a first region and a second region;

a dummy gate electrode disposed on the first region of the field insulation layer;

a gate electrode crossing the multi-channel active pattern, the gate electrode being disposed on the second region of the field insulation layer, the gate electrode having a height greater than that of the dummy gate electrode; and

a source or drain disposed between the gate electrode and the dummy gate electrode and including a facet,

wherein the facet is adjacent to a sidewall of the first region of the field insulation layer.

10. The semiconductor device of claim 9 , wherein a material interposed between the facet and the sidewall of the first region of the field insulation layer is different from a material of the multi-channel active pattern.

11. The semiconductor device of claim 9 , wherein a height of the first region of the field insulation layer is greater than a height of the second region of the field insulation layer.

12. A semiconductor device, comprising:

a multi-channel active pattern;

a field insulation layer disposed on first and second sides of the multi-channel active pattern, the field insulation layer including a first region extending to a top surface of the multi-channel active pattern;

a gate electrode overlapping the multi-channel active pattern and disposed on the field insulation layer on the first and second sides of the multi-channel active pattern; and

a source or drain disposed between the gate electrode and the first region of the field insulation layer, the source or drain including a slanted edge that extends from the first region of the field insulation layer to a spacer adjacent to the gate electrode.

13. The semiconductor device of claim 12 , wherein a material different from a material of the multi-channel active pattern is disposed in an area adjacent to the edge of the source or drain.

14. The semiconductor device of claim 13 , wherein a sidewall of the first region of the field insulation layer forms a side of the area adjacent to the edge of the source or drain.

15. The semiconductor device of claim 14 , wherein an insulation pattern is disposed along the side of the area adjacent to the edge of the source or drain.

16. The semiconductor device of claim 12 , wherein a dummy gate electrode is disposed on the first region of the field insulation layer.