Device including single wire interface and data processing system including the same
A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
1. A master device which communicates with a slave device, the master device comprising:
a single pad configured to communicate a command frame including an address and a data frame, the data frame including data, with the slave device via a single wire; and
a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using the same clock phase as the clock phase selected during the synchronization process.
2. The master device of claim 1 , wherein each of the command frame and the data frame comprises a start bit value and a stop bit value and the processing circuit configured to perform the synchronization process on the start bit value.
3. The master device of claim 1 , wherein the processing circuit comprises:
a sync detection circuit; and
a data processing circuit,
wherein the sync detection circuit configured to generate a plurality of clock phase selection signals related to the selected clock phase in each period of the oversampling clock signal and the data processing circuit configured to sample the each bit value included in the data frame in the each period of the oversampling clock signal using a clock phase related to the plurality of clock phase selection signals.
4. The master device of claim 3 , wherein the oversampling clock signal is a 4× oversampling clock signal.
5. The master device of claim 3 , wherein the oversampling clock signal is a 2× oversampling clock signal.
6. The master device of claim 1 , wherein the single wire does not comprise a clock line configured to transmit the clock signal to the slave device.
7. The master device of claim 1 , wherein the master and slave devices have clock signals of the same frequency.
8. The master device of claim 1 , further comprising:
a pull-up resistor configured to control connection between a voltage supply line and the single pad in response to a pull-up resistor enable signal; and
an output driver connected to the single pad.
9. The master device of claim 8 , further comprising a control circuit configured to activate the pull-up resistor enable signal when a stop bit value included in the command frame is transmitted to the single pad through the output driver.
10. The master device of claim 1 , further comprising a frame generator configured to generate the command frame including a parity bit.
11. A slave device which communicates with a master device, the slave device comprising:
a single pad configured to communicate a command frame including an address and a data frame including data with the master device via a single wire; and
a processing circuit configured to generate an oversampling clock signal from a clock signal, to select one clock phase from among a plurality of clock phases of the oversampling clock signal, and to sample an each bit value included in the data frame transmitted from the master device using the one clock phase.
12. The slave device of claim 11 , wherein the processing circuit comprises:
a sync detection circuit; and
a data processing circuit,
wherein the sync detection circuit configured to generate a plurality of clock phase selection signals related to the one clock phase in each period of the oversampling clock signal and the data processing circuit configured to sample the each bit value included in the data frame in each period of the oversampling clock signal using the one clock phase related to the plurality of clock phase selection signals.
13. The slave device of claim 12 , wherein the oversampling clock signal is a 4× oversampling clock signal.
14. The slave device of claim 12 , wherein the oversampling clock signal is a 2× oversampling clock signal.
15. The slave device of claim 11 , wherein the single wire does not comprise a clock line configured to transmit the clock signal.
16. A master device that communicates with a slave device, comprising:
a processing circuit configured to communicate a command frame and a data frame through a single asynchronous serial link with the slave device; and
a single pad configured to output the command frame and the data frame to the single asynchronous serial link,
wherein the command frame includes a burst frame and a random frame allowing burst transmission of stream data from the master device to the slave device, wherein the single asynchronous serial link does not comprise a clock line configured to transmit a clock signal to the slave device.
17. The master device of claim 16 , wherein the processing circuit is further configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
18. The master device of claim 17 , wherein the processing circuit comprises:
a sync detection circuit; and
a data processing circuit,
wherein the sync detection circuit configured to generate a plurality of clock phase selection signals related to the selected clock phase in each period of the oversampling clock signal and the data processing circuit configured to sample the each bit value included in the data frame in the each period of the oversampling clock signal using a clock phase related to the plurality of clock phase selection signals.
19. The master device of claim 18 , further comprising:
a pull-up resistor configured to control connection between a voltage supply line and a single pad through which asynchronous serial communication flows in response to a pull-up resistor enable signal; and
an output driver connected to the single pad.
20. The master device of claim 19 , further comprising a control circuit configured to activate the pull-up resistor enable signal when a stop bit value included in the command frame is transmitted to the single pad through the output driver.