Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.
1. A method comprising:
providing a plate including a number of solid glass layers bonded together, the plate having a first surface and an opposing second surface;
forming a first via in a first solid glass layer of the number of solid glass layers;
disposing a protective layer on a wall of the first via; and
forming a second via in a second solid glass layer adjacent the first solid glass layer, the first via generally aligned with the second via, the first and second vias forming at least part of a hole extending from the first surface to the second surface.
2. The method of claim 1 , further comprising removing the protective layer.
3. The method of claim 2 , further comprising:
depositing a seed layer over a wall of the hole; and
plating a metal over the seed layer to provide a conductor within the hole.
4. The method of claim 3 , further comprising disposing a dielectric material in the hole over the metal plating.
5. The method of claim 3 , further comprising
disposing at least one dielectric layer and at least one metal layer at the first surface of the plate and electrically coupling the at least one metal layer at the first surface with the conductor; and
disposing at least one dielectric layer and a least one metal layer at the second surface of the plate and electrically coupling the at least one metal layer at the second surface with the conductor.
6. The method of claim 5 , further comprising:
disposing a first set of terminals at the first side of the plate, the first set of terminals to mate with a corresponding array of terminals on an integrated circuit (IC) die; and
disposing a second set of terminals at the second side of the plate, the second set of terminals to mate with a corresponding array of terminals on a next-level component.
7. The method of claim 5 , wherein the at least one metal layer disposed at the first surface of the plate is disposed directly adjacent the first surface, and wherein the at least one metal layer disposed at the second surface of the plate is disposed directly adjacent the second surface.
8. The method of claim 1 , wherein the first solid glass layer is coupled with the second solid glass layer by a bonding layer, the method further comprising forming a via in the bonding layer, the via of the bonding layer forming part of the hole.
9. The method of claim 1 , wherein disposing the protective layer on the wall of the first via comprises disposing a material selected from the group consisting of an organic material, a metal, a metal oxide, and silicon nitride.
10. The method of claim 1 , wherein disposing the protective layer on the wall of the first via comprises disposing the protective layer on the wall of the first via by atomic layer deposition.
11. The method of claim 1 , wherein disposing the protective layer on the wall of the first via comprises disposing the protective layer on the wall of the first via by chemical vapor deposition.
12. The method of claim 1 , wherein forming the first via in the first solid glass layer of the number of solid glass layers comprises etching the first via in the first solid glass layer of the number of solid glass layers.
13. The method of claim 12 , wherein etching the first via in the first solid glass layer of the number of solid glass layers comprises wet etching the first via in the first solid glass layer of the number of solid glass layers.
14. The method of claim 12 , wherein etching the first via in the first solid glass layer of the number of solid glass layers comprises dry etching the first via in the first solid glass layer of the number of solid glass layers.
15. The method of claim 1 , wherein forming the second via in the second solid glass layer of the number of solid glass layers comprises etching the second via in the second solid glass layer of the number of solid glass layers through the first via in the first solid glass layer of the number of solid glass layers.
16. The method of claim 15 , wherein etching the second via in the second solid glass layer of the number of solid glass layers through the first via in the first solid glass layer of the number of solid glass layers comprises wet etching the second via in the second solid glass layer of the number of solid glass layer through the first via in the first solid glass layer of the number of solid glass layers.
17. The method of claim 15 , wherein etching the second via in the second solid glass layer of the number of solid glass layers through the first via in the first solid glass layer of the number of solid glass layers comprises wet etching the second via in the second solid glass layer of the number of solid glass layer through the first via in the first solid glass layer of the number of solid glass layers.