Access signal conditioning for memory cells in an array
A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a disturb isolator circuit operatively coupled to the MEs to compensate for disturbances of a magnitude of a signal associated with a selected two-terminal resistive memory element in the array.
1. An apparatus, comprising:
an array comprising two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power; and
a disturb isolator circuit operatively coupled to the MEs to compensate for disturbances of a magnitude of a signal associated with a selected two-terminal resistive memory element in the array.
2. The apparatus of claim 1 , where the disturbances are attributable to electrical or electromagnetic coupling on the selected two-terminal resistive memory element.
3. The apparatus of claim 1 , further comprising a positional characteristic adjuster coupled with the disturb isolator circuit.
4. The apparatus of claim 3 , wherein the positional characteristic adjuster is configured to determine the magnitude of the signal as a function of a distance between a position of the selected two-terminal resistive memory and the disturb isolator.
5. The apparatus of claim 1 , wherein the positional characteristic adjuster is configured to modify the magnitude based on an indicator signal.
6. The apparatus of claim 5 , wherein the positional characteristic adjuster is configured to modify the magnitude based on an indicator signal via a feedback path, wherein the indictor signal represents the magnitude of the signal at a location in the array.
7. The apparatus of claim 1 , wherein the signal is a read voltage signal and wherein the disturb isolator circuit is configured to compensate for disturbances of the magnitude of the read voltage signal associated with a particular word line of the array.
8. The apparatus of claim 7 , wherein the disturbances is caused by repeated applications of read voltages to the array.
9. The apparatus of claim 7 , wherein the magnitude is a target read voltage magnitude and wherein the disturb isolation circuit is configured to reduce the target read voltage magnitude.
10. The apparatus of claim 9 , wherein the disturb isolation circuit is configured to reduce the target read voltage magnitude to approximate one-half the target read voltage magnitude.
11. The apparatus of claim 7 , wherein the disturb isolation circuit is configured to reduce the magnitude of the read voltage signal while maintaining an access current equivalent to that associated with a first magnitude of the read voltage signal.
12. The apparatus of claim 9 , wherein the disturb isolation circuit comprises a current enhancement array configured to generate an amount of current at a portion of the target read voltage magnitude.
13. The apparatus of claim 9 , wherein the current enhancement array comprises a plurality of resistive memory elements coupled in parallel.
14. A method comprising:
identifying a selected two-terminal resistive memory element in an array comprising a plurality of two-terminal memory elements, to retain stored data in an absence of electrical power; and
conditioning an access signal to access the selected two-terminal resistive memory element in the array while isolating disturb effects on unselected two-terminal resistive memory elements in the array.
15. The method of claim 14 , further comprising determining the magnitude of the signal as a function of a distance between a position of the selected two-terminal resistive memory and a disturb isolator circuit.
16. The method of claim 14 , further comprising modifying the magnitude based on an indicator signal via a feedback path, wherein the indictor signal represents the magnitude of the signal at a location in the array.
17. The method of claim 14 , wherein the signal is a read voltage signal and wherein the method further comprises compensating for disturbances of the magnitude of the read voltage signal associated with a particular word line of the array.
18. The method of claim 17 , wherein the magnitude is a target read voltage magnitude and wherein the method comprises reducing the target read voltage magnitude.
19. The method of claim 18 , wherein reducing the target read voltage magnitude comprises reducing the read voltage magnitude to approximate one-half the target read voltage magnitude.
20. The method of claim 17 , wherein the method comprises reducing the magnitude of the read voltage signal while maintaining an access current equivalent to that associated with a first magnitude of the read voltage signal.
21. The method of claim 17 , further comprising generating an amount of current at a portion of the target read voltage magnitude.