IP Library Granted Patent US 9,769,411
Granted Patent B2
US 9,769,411 · App. 15/180,300 · Granted Sep 19, 2017

Solid-state image pickup device and method for driving the same in solid-state imaging pickup device and method for driving the same in a number of modes

Inventors: Yoshikazu Nitta (Tokyo, JP); Noriyuki Fukushima (Kanagawa, JP); Yoshinori Muramatsu (Kanagawa, JP); Yukihiko Yasui (Kanagawa, JP)
Assignee: Sony Corporation
H04N5/378H03M1/1023H04N3/1562H04N5/2253H04N5/347H04N5/37455H03M1/56
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Quick Facts
Patent No.
US 9,769,411
App. No.
15/180,300
Granted
Sep 19, 2017
Kind
B2
Abstract

A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

Claims (50)

1. An imaging device comprising:

a pixel array unit including a plurality of pixels which are two-dimensionally arranged in columns and rows;

a plurality of signal lines including a first signal line coupled to a first pixel of the plurality of pixels and a second signal line between the first signal line and a third signal line;

a plurality of analog-to-digital (A/D) converters, each A/D converter of the plurality of A/D converters including a comparator, a counter, and a memory;

a plurality of switch circuits;

a first comparator of a first A/D converter coupled to the first signal line; and

a second comparator of a second A/D converter selectively coupled to the second signal line or the third signal line through a first switch circuit of the plurality of switch circuits,

wherein,

the first comparator is configured to output a first signal based on an output of the first signal line,

the second comparator is configured to output a second signal based on an output of the third signal line at a same time the first comparator is configured to output the first signal based on the output of the first signal line, and

the memory of the second A/D converter is configured to receive a third signal based on the second signal.

2. The imaging device according to claim 1 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator.

3. The imaging device according to claim 1 , wherein the memory of the second A/D converter is coupled to a counter of the second A/D converter.

4. The imaging device according to claim 3 , wherein the memory of the second A/D converter is configured to receive the third signal based on the second signal through the counter of the second A/D converter.

5. The imaging device according to claim 4 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

6. The imaging device according to claim 1 , further comprising a third comparator selectively coupled to the third signal line through a second switch circuit of the plurality of switch circuits.

7. An imaging device comprising:

a pixel array unit including a plurality of pixels which are two-dimensionally arranged in columns and rows;

a plurality of signal lines including a first signal line coupled to a first pixel of the plurality of pixels and a second signal line between the first signal line and a third signal line;

a plurality of analog-to-digital (A/D) converters, each A/D converter of the plurality of A/D converters including a comparator, a counter, and a memory;

a plurality of switch circuits;

a first comparator of a first A/D converter coupled to the first signal line; and

a second comparator of a second A/D converter selectively coupled to the second signal line or the third signal line through a first switch circuit of the plurality of switch circuits,

wherein,

the first A/D converter is configured to output a first signal based on an output of the first signal line, and

the second A/D converter is configured to output a second signal based on an output of the third signal line at a same time the first A/D converter is configured to output the first signal based on the output of the first signal line.

8. The imaging device according to claim 7 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator.

9. The imaging device according to claim 7 , wherein memory of the second A/D converter is coupled to a counter of the second A/D converter.

10. The imaging device according to claim 9 , wherein the memory of the second A/D converter is configured to receive a third signal based on the second signal through the counter of the second A/D converter.

11. The imaging device according to claim 10 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

12. The imaging device according to claim 7 , further comprising a third comparator selectively coupled to the third signal line through a second switch circuit of the plurality of switch circuits.

13. The imaging device according to claim 7 , further comprising an output line connected to a signal processing circuit.

14. An electronic apparatus comprising;

an optical system; and

an imaging device including:

a pixel array unit including a plurality of pixels which are two-dimensionally arranged in columns and rows,

a plurality of signal lines including a first signal line coupled to a first pixel of the plurality of pixels and a second signal line between the first signal line and a third signal line,

a plurality of analog-to-digital (A/D) converters, each A/D converter of the plurality of A/D converters including a comparator, a counter, and a memory,

a plurality of switch circuits,

a first comparator of a first A/D converter coupled to the first signal line, and

a second comparator of a second A/D converter selectively coupled to the second signal line or the third signal line through a first switch circuit of the plurality of switch circuits,

wherein,

the first A/D converter is configured to output a first signal based on an output of the first signal line, and

the second A/D converter is configured to output a second signal based on an output of the third signal line at a same time the first A/D converter is configured to output the first signal based on the output of the first signal line.

15. The electronic apparatus according to claim 14 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator.

16. The electronic apparatus according to claim 14 , wherein memory of the second A/D converter is coupled to a counter of the second A/D converter.

17. The electronic apparatus according to claim 16 , wherein the memory of the second A/D converter is configured to receive a third signal based on the second signal through the counter of the second A/D converter.

18. The electronic apparatus according to claim 17 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

19. The electronic apparatus according to claim 14 , further comprising a third comparator selectively coupled to the third signal line through a second switch circuit of the plurality of switch circuits.

20. The electronic apparatus according to claim 14 , further comprising an output line connected to a signal processing circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2020
From: NITTA, YOSHIKAZU; FUKUSHIMA, NORIYUKI; MURAMATSU, YOSHINORI; YASUI, YUKIHIKO
To: SONY CORPORATION
Reel/Frame 052710/0496 →
Priority Claims (2)
JP 2004-045943 · Feb 23, 2004 · national
JP 2004-208038 · Jul 15, 2004 · national
Continuity (8)
Continuation 14957407 · Dec 2, 2015
Continuation 14294942 · Jun 3, 2014
Continuation 14023239 · Sep 10, 2013
Continuation 13094420 · Apr 26, 2011
Continuation 12772573 · May 3, 2010
Continuation 12419077 · Apr 6, 2009
Division 11058851 · Feb 16, 2005
Related Publication 20160295145A1 · Oct 6, 2016