Method of preparation of III-V compound layer on large area Si insulating substrate
A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.
1. A method for preparing a III-V compound substrate on an insulator, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a first trench on the first dielectric layer to expose the substrate;
forming a sacrificial layer on the first dielectric layer, the sacrificial layer covering a first portion of the first dielectric layer and filling the first trench;
forming a second dielectric layer on the sacrificial layer, the second dielectric layer covering the sacrificial layer and a second portion of the first dielectric;
on the second dielectric layer forming a groove such that an opening of the groove exposes the sacrificial layer, wherein the groove does not penetrate into the sacrificial layer;
removing the sacrificial layer through the opening of the groove, wherein a cavity is formed between the first dielectric layer and the second dielectric layer;
growing III-V compounds to fill the first trench and the cavity;
removing the second dielectric layer;
removing the III-V compounds filled in the cavity to form a second trench, the second trench being above the first trench;
removing the III-V compounds filled in the first trench; and
filling the first trench with a first dielectric layer, and the second trench with a III-V compound.
2. The method of claim 1 , wherein a material of the III-V compound substrate is GaN, InP, InAs, InSb, or InGaAs.
3. The method of claim 2 , wherein the III-V compound substrate is prepared using metal organic chemical vapor deposition, atomic layer deposition or molecular beam epitaxy.
4. The method of claim 1 , wherein the said substrate is a single crystal silicon substrate.
5. The method of claim 1 , wherein the sacrificial layer is amorphous carbon, germanium or silicon-germanium alloy, having a thickness in the range of from 5 nm to 100 nm.
6. The method of claim 1 , wherein the sacrificial layer is removed by plasma etching.
7. The method of claim 1 , wherein said first dielectric layer is silicon oxide, having a thickness in the range of from 5 nm to 100 nm.
8. The method of claim 1 , wherein said second dielectric layer is silicon nitride, having a thickness in the range of from 5 nm to 100 nm.
9. The method of claim 1 , wherein said a width of the second trench is greater than a width of the first trench.
10. The method of claim 9 , wherein the width of the first trench is in the range of from 50 nm to 500 nm, the width of the second trench is in the range of from 100 nm to 1000 nm.