IP Library › Granted Patent US 9,773,770
Granted Patent B2
US 9,773,770 · App. 14/864,903 · Granted Sep 26, 2017

Semiconductor device

Inventors: Kei-Kang Hung (Hsinchu County, TW); Chih-Hao Chen (Hsinchu County, TW)
Assignee: UBIQ Semiconductor Corp.
H01L27/0207H01L27/0814H01L27/092
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Quick Facts
Patent No.
US 9,773,770
App. No.
14/864,903
Granted
Sep 26, 2017
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate and a first semiconductor element. The semiconductor substrate has a circuit core area. The first semiconductor element is arranged on the semiconductor substrate and at least partially surrounds the periphery of the circuit core area. A layout area of the first semiconductor element is larger than a layout area of any of the semiconductor elements in the circuit core area.

Claims (46)

1. A semiconductor device comprising:

a semiconductor substrate having a circuit core area; and

a first semiconductor element arranged on the semiconductor substrate, the first semiconductor element at least partially surrounding a periphery of the circuit core area, wherein a layout area of the first semiconductor element is larger than a layout area of any of semiconductor elements in the circuit core area, wherein the any of the semiconductor elements in the circuit core area comprises:

a power pad, wherein the power pad is electrically connected to a first connection portion of the first semiconductor element; and

a signal pad.

2. The semiconductor device of claim 1 , wherein the layout area of the first semiconductor element is at least twice the layout area of any of semiconductor elements in the circuit core area.

3. The semiconductor device of claim 1 , wherein the first semiconductor element is a Zener diode or a power transistor.

4. The semiconductor device of claim 1 , wherein the first semiconductor element is shaped as a letter C or a ring and surrounds the periphery of the circuit core area.

5. A semiconductor device, comprising:

a semiconductor substrate having a circuit core area; and

a first semiconductor element arranged on the semiconductor substrate, the first semiconductor element at least partially surrounding a periphery of the circuit core area, wherein a layout area of the first semiconductor element is larger than a layout area of any of semiconductor elements in the circuit core area,

wherein the first semiconductor element comprises:

a first-electrode line arranged on the semiconductor substrate and shaped as a letter C or a ring, the first-electrode line at least partially surrounding the periphery of the circuit core area, wherein a first connection portion of the first-electrode line is electrically connected to a first power pad via a power rail;

a second-electrode ring arranged on the semiconductor substrate, the second-electrode ring at least partially surrounding the periphery of the circuit core area, wherein a second connection portion of the second-electrode ring is electrically connected to a second power pad; and

a second-electrode line arranged on the semiconductor substrate and shaped as a letter L, the letter C, or a ring, the second-electrode line surrounding the periphery of the circuit core area, wherein the second-electrode line is electrically connected to the second power pad, and

the first-electrode line is arranged between the second-electrode ring and the second-electrode line.

6. The semiconductor device of claim 1 , wherein the any of the semiconductor elements in the circuit core area comprises a diode or a driving controller.

7. A semiconductor device, comprising:

a semiconductor substrate having a circuit core area; and

a first semiconductor element arranged on the semiconductor substrate, the first semiconductor element at least partially surrounding a periphery of the circuit core area, wherein a layout area of the first semiconductor element is larger than a layout area of any of semiconductor elements in the circuit core area,

wherein the any of the semiconductor elements in the circuit core area comprises:

a first power pad arranged above the semiconductor substrate and located in the circuit core area, wherein the first power pad is electrically connected to a first connection portion of the first semiconductor element via a power rail;

a second power pad arranged above the semiconductor substrate and located on an edge portion of the circuit core area, wherein the second power pad is electrically connected to a second connection portion of the first semiconductor element;

a signal pad arranged above the semiconductor substrate and located in the circuit core area;

a first diode arranged in the circuit core area and located between the first power pad and the signal pad, wherein a first terminal of the first diode is electrically connected to the first power pad, and a second terminal of the first diode is electrically connected to the signal pad; and

a second diode arranged in the circuit core area and located between a third connection portion of the first semiconductor element and the signal pad, wherein a first terminal of the second diode is electrically connected to the signal pad, and a second terminal of the second diode is electrically connected to the third connection portion of the first semiconductor element.

8. The semiconductor device of claim 7 , wherein the first diode comprises:

a plurality of first electrodes acting as the first terminal of the first diode, the first electrodes being electrically connected to the first power pad; and

a plurality of second electrodes acting as the second terminal of the first diode, the second electrodes being electrically connected to the signal pad, wherein the first electrodes and the second electrodes are alternately arranged as fingers.

9. The semiconductor device of claim 7 , wherein the third connection portion of the first semiconductor element is electrically connected to the second connection portion of the first semiconductor element via a metal conductive wire.

10. The semiconductor device of claim 1 , wherein

the power pad is arranged above the semiconductor substrate and located in the circuit core area,

the signal pad is arranged above the semiconductor substrate and located in the circuit core area and between the first semiconductor element and the power pad, and the any of the semiconductor elements in the circuit core area further comprises:

a first diode arranged in the circuit core area and located between the power pad and the signal pad, wherein a first terminal of the first diode is electrically connected to the power pad, and a second terminal of the first diode is electrically connected to the signal pad; and

a second diode arranged in the circuit core area and located between a second connection portion of the first semiconductor element and the signal pad, wherein a first terminal of the second diode is electrically connected to the signal pad, and a second terminal of the second diode is electrically connected to the second connection portion of the first semiconductor element.

11. The semiconductor device of claim 10 , wherein the first diode comprises:

a first electrode acting as the first terminal of the first diode, the first electrode being electrically connected to the power pad; and

a second electrode acting as the second terminal of the first diode, the second electrode being electrically connected to the signal pad, wherein the second electrode is shaped as a letter C and surrounds a periphery of the first electrode.

12. The semiconductor device of claim 1 , further comprising:

a second semiconductor element arranged on the semiconductor substrate, the second semiconductor element surrounding the periphery of the circuit core area, wherein a layout area of the second semiconductor device is larger than the layout area of any of semiconductor devices in the circuit core area.

13. The semiconductor device of claim 12 , wherein the second semiconductor element is a Zener diode or a power transistor.

14. The semiconductor device of claim 12 , wherein the first semiconductor element and the second semiconductor element are respectively shaped as a letter C and surround the periphery of the circuit core area.

15. The semiconductor device of claim 12 , wherein the second semiconductor element comprises:

a gate line arranged on the semiconductor substrate and shaped as a letter C or a ring, the gate line surrounding the periphery of the circuit core area;

a source line arranged on the semiconductor substrate and shaped as the letter C or a ring, the source line surrounding the periphery of the circuit core area; and

a drain line arranged on the semiconductor substrate and shaped as the letter C or a ring, the drain line surrounding the periphery of the circuit core area, wherein the gate line is located between the source line and the drain line.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2021
From: UPI SEMICONDUCTOR CORP.
To: IPU SEMICONDUCTOR CO., LTD.
Reel/Frame 054805/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2018
From: UBIQ SEMICONDUCTOR CORP.
To: UPI SEMICONDUCTOR CORP.
Reel/Frame 046376/0094 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2015
From: HUNG, KEI-KANG; CHEN, CHIH-HAO
To: UBIQ SEMICONDUCTOR CORP.
Reel/Frame 036699/0517 →
Priority Claims (1)
TW 104109986 A · Mar 27, 2015 · national
Continuity (1)
Related Publication 20160284692A1 · Sep 29, 2016