Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance
Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.
1. An integrated circuit (IC), comprising:
a substrate;
a plurality of inter-layer dielectrics (ILDs) comprised of a dielectric material, the plurality of ILDs disposed above the substrate, wherein at least one of the plurality of ILDs comprises a first region and a second region in a same layer; and
a plurality of circuits comprised of at least one critical path element and at least one non-critical path element, each of the plurality of circuits comprising:
a plurality of semiconductor elements disposed in at least one first ILD among the plurality of ILDs; and
at least one circuit element interconnect disposed in at least one second ILD among the plurality of ILDs, the at least one circuit element interconnect conductively coupled to at least one semiconductor element among the plurality of semiconductor elements;
wherein the first region in which the at least one non-critical path element is disposed comprises a first K dielectric material, wherein the first region is positioned directly above at least one of the plurality of semiconductor elements; and
wherein the second region in which the at least one critical path element is disposed comprises a second K dielectric material comprised of a low-K dielectric material having a lower K value than the first K dielectric material, and wherein the second region is positioned directly above at least another one of the plurality of semiconductor elements.
2. The IC of claim 1 , wherein the low-K dielectric material is comprised of a dielectric material having a K value lower than 3.5.
3. The IC of claim 1 , wherein the low-K dielectric material is comprised of a porous low-K dielectric material.
4. The IC of claim 1 , wherein the low-K dielectric material is comprised of an air gap.
5. The IC of claim 1 , wherein the low-K dielectric material is comprised of a doped low-K dielectric material.
6. The IC of claim 5 , wherein the doped low-K dielectric material is comprised from the group consisting of: a carbon-doped low-K dielectric material and a flourene-doped low-K dielectric material.
7. The IC of claim 1 , wherein the low-K dielectric material is comprised of a low-K polymeric dielectric material.
8. The IC of claim 1 , wherein the at least a second region of the plurality of ILDs that comprises the low-K dielectric material comprises only one or more ILDs that only contain the at least one circuit element interconnect.
9. The IC of claim 1 , wherein the first K dielectric material is not comprised of a low-K dielectric material.
10. The IC of claim 1 , wherein the first K dielectric material is comprised of a low-K dielectric material.
11. The IC of claim 1 integrated into a multiple processor core central processing unit (CPU).
12. The IC of claim 1 integrated into a system-on-a-chip (SoC).
13. The IC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.
14. An integrated circuit (IC), comprising:
a means for providing a substrate;
a plurality of inter-layer dielectrics (ILDs) comprised of a dielectric material, the plurality of ILDs disposed above the means for providing the substrate, wherein at least one of the plurality of ILDs comprises a first region and a second region in a same layer; and
a plurality of circuit means comprised of at least one critical path means and at least one non-critical path means, each of the plurality of circuit means comprising:
a plurality of semiconductor means disposed in at least one means for providing a first ILD among the plurality of ILDs; and
at least one means for providing a circuit element interconnect disposed in at least one means for providing a second ILD among the plurality of ILDs, the at least one means for providing the circuit element interconnect conductively coupled to at least one semiconductor means among the plurality of semiconductor means;
wherein the first region in which the at least one non-critical path means is disposed comprises a first K dielectric material; and
wherein the second region in which the at least one critical path means is disposed comprises a second K dielectric material comprised of a low-K dielectric material having a lower K value than the first K dielectric material.