Self aligned gate shape preventing void formation
A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
1. A method of forming a semiconductor device comprising:
forming a replacement gate structure in contact with a first device channel and a second device channel, wherein the replacement gate structure includes a sacrificial gate conductor and a dielectric cap layer that includes a bump portion between the first and second semiconductor device channel;
removing the bump portion of the dielectric cap layer and the underlying portion of the sacrificial gate conductor to provide an isolation gate opening having a first width between the first and second device channels;
removing the portion of the replacement gate structure over the first and second device channels to provide functional gate openings having a second gate width that is less than the first gate width; and
forming a first and second functional gate structure in the functional gate openings to the first and second semiconductor device channels.
2. The method of claim 1 , wherein the first device channel is provided by a first fin structure and the second device channel is provided by a second fin structure.
3. The method of claim 2 , wherein the first fin structure is separated from the second fin structure by an isolation region, wherein said isolation gate opening is formed over the isolation region.
4. The method of claim 2 , further comprising forming an interlevel dielectric layer having an upper surface coplanar with an upper surface of the bump portion.
5. The method of claim 4 , wherein the dielectric cap layer is present on sidewalls of the portion of the sacrificial gate conductor that is present on the isolation region and extends to the bump portion of the dielectric cap layer that is present on the upper surface of the sacrificial gate conductor.
6. The method of claim 5 , wherein the removing of the bump portion of the dielectric cap layer and the underlying portion of the sacrificial gate conductor to provide an isolation gate opening having a first width between the first and second device channels comprises:
removing the bump portion of the dielectric cap layer with an anisotropic etch that is selective to at least the isolation gate structure; and
removing the underlying portion of the sacrificial gate conductor with an etch process that tapers an inside sidewall of the dielectric cap layer that is present on sidewalls of the portion of the sacrificial gate conductor.
7. The method of claim 6 , wherein a portion of the dielectric cap layer that is present on the sacrificial gate conductor over the first fin structure and the second fin structure has a lesser height than a height of the bump portion of the dielectric cap layer prior to being removed.
8. The method of claim 7 , wherein said removing the portion of the replacement gate structure over the first and second device channels to provide functional gate openings having a second gate width that is less than the first gate width comprises:
forming amorphous semiconductor material in the isolation gate opening;
planarizing the interlevel dielectric layer to remove an upper portion of the dielectric cap layer to expose the portion of the sacrificial gate conductor that is present over the first fin structure and the second fin structure; and
removing the sacrificial gate conductor over the first fin structure and the second fin structure with an etch that is selective to a remaining portion of the dielectric cap layer that is present contacting sidewalls of the sacrificial gate conductor over the first fin structure and the second fin structure, and the amorphous semiconductor material in the isolation gate opening.
9. The method of claim 8 , wherein forming the first and second functional gate structure in the functional gate openings to the first and second semiconductor device channels comprises:
removing the amorphous semiconductor material in the isolation gate opening;
forming a gate dielectric in the isolation gate opening, the first functional gate opening and the second functional gate opening;
forming a first work function metal in the isolation gate opening, the first functional gate opening and the second functional gate opening;
forming a block mask filling at least a portion of the first functional gate opening, and completely filling the isolation gate opening;
removing exposed portions of at least the first work function metal in the second functioning gate opening; and
forming a second work function metal in at least the second functional gate opening.
10. A method of forming a semiconductor device comprising:
forming a replacement gate structure in contact with a first fin structure and a second fin structure that are present on a semiconductor substrate and separated by an isolation region, wherein the replacement gate structure includes a sacrificial gate conductor and a dielectric cap layer that includes a bump portion overlying the isolation region between the first and second fin structures;
removing the bump portion of the dielectric cap layer and the underlying portion of the sacrificial gate conductor to provide an isolation gate opening having a first width between the first and second fin structures;
removing the portion of the replacement gate structure over the first and second fin structures to provide functional gate openings having a second gate width that is less than the first gate width; and
forming a first and second functional gate structure in the functional gate openings to the first and second fin structures.
11. The method of claim 10 , further comprising forming an interlevel dielectric layer having an upper surface coplanar with an upper surface of the bump portion.
12. The method of claim 11 , wherein the dielectric cap layer is present on sidewalls of the portion of the sacrificial gate conductor that is present on the isolation region and extends to the bump portion of the dielectric cap layer that is present on the upper surface of the sacrificial gate conductor.
13. The method of claim 12 , wherein the removing of the bump portion of the dielectric cap layer and the underlying portion of the sacrificial gate conductor to provide an isolation gate opening having a first width between the first and second device channels comprises:
removing the bump portion of the dielectric cap layer with an anisotropic etch that is selective to at least the isolation gate structure; and
removing the underlying portion of the sacrificial gate conductor with an etch process that tapers an inside sidewall of the dielectric cap layer that is present on sidewalls of the portion of the sacrificial gate conductor.
14. The method of claim 13 , wherein a portion of the dielectric cap layer that is present on the sacrificial gate conductor over the first fin structure and the second fin structure has a lesser height than a height of the bump portion of the dielectric cap layer prior to being removed.
15. The method of claim 14 , wherein said removing the portion of the replacement gate structure over the first and second device channels to provide functional gate openings having a second gate width that is less than the first gate width comprises:
forming amorphous semiconductor material in the isolation gate opening;
planarizing the interlevel dielectric layer to remove an upper portion of the dielectric cap layer to expose the portion of the sacrificial gate conductor that is present over the first fin structure and the second fin structure; and
removing the sacrificial gate conductor over the first fin structure and the second fin structure with an etch that is selective to a remaining portion of the dielectric cap layer that is present contacting sidewalls of the sacrificial gate conductor over the first fin structure and the second fin structure, and the amorphous semiconductor material in the isolation gate opening.
16. The method of claim 15 , wherein forming the first and second functional gate structure in the functional gate openings to the first and second semiconductor device channels comprises:
removing the amorphous semiconductor material in the isolation gate opening;
forming a gate dielectric in the isolation gate opening, the first functional gate opening and the second functional gate opening;
forming a first work function metal in the isolation gate opening, the first functional gate opening and the second functional gate opening;
forming a block mask filling at least a portion of the first functional gate opening, and completely filling the isolation gate opening;
removing exposed portions of at least the first work function metal in the second functioning gate opening; and
forming a second work function metal in at least the second functional gate opening.
17. The method of claim 16 further comprising removing the block mask prior to forming the second work function metal.