IP Library Granted Patent US 9,773,890
Granted Patent B2
US 9,773,890 · App. 14/919,716 · Granted Sep 26, 2017

Semiconductor device and method of fabricating the same

Inventors: Chia-Lin Lu (Taoyuan, TW); Chun-Lung Chen (Tainan, TW); Kun-Yuan Liao (Hsin-Chu, TW); Feng-Yi Chang (Tainan, TW); Wei-Hao Huang (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66795H01L21/26513H01L21/76897H01L29/785
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Quick Facts
Patent No.
US 9,773,890
App. No.
14/919,716
Granted
Sep 26, 2017
Kind
B2
Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

Claims (17)

1. A semiconductor device, comprising:

a fin shaped structure disposed on a substrate;

a gate structure across the fin shaped structure, the gate structure comprising a spacer;

an epitaxial layer disposed in the fin shaped structure adjacent to the gate structure;

an interlayer dielectric layer covering the substrate and the fin shaped structure;

an opening disposed in the interlayer dielectric layer, to expose the epitaxial layer;

a first plug formed in the opening, wherein the first plug is electrically connected to the epitaxial layer; and

a protection layer covering entire sidewalls of the opening between the first plug and the gate structure, wherein a portion of the protection layer is sandwiched between the spacer of the gate structure and the epitaxial layer in a horizontal plane.

2. The semiconductor device according to claim 1 , wherein the protection layer comprises an insulating material.

3. The semiconductor device according to claim 1 , wherein the protection layer comprises SiN or SiCN.

4. The semiconductor device according to claim 1 , wherein the protection layer has a thickness between about 10 angstroms to 15 angstroms.

5. The semiconductor device according to claim 1 , wherein the first plug comprises a first barrier layer and a first contact metal layer.

6. The semiconductor device according to claim 5 , wherein the first barrier layer directly contacts the protection layer and the epitaxial layer.

7. The semiconductor device according to claim 1 , further comprising:

a second plug formed in the interlayer dielectric layer to contact the gate structure.

8. The semiconductor device according to claim 7 , wherein the second plug comprises a second barrier layer and a second contact metal, and the second barrier layer directly contacts the interlayer dielectric layer.

9. The semiconductor device according to claim 1 , wherein the epitaxial layer comprises SiC, SiP, SiCP, SiGe or Ge.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2015
From: LU, CHIA-LIN; CHEN, CHUN-LUNG; LIAO, KUN-YUAN; CHANG, FENG-YI; HUANG, WEI-HAO
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036850/0967 →
Priority Claims (1)
TW 104131396 A · Sep 23, 2015 · national
Continuity (1)
Related Publication 20170084722A1 · Mar 23, 2017