Multi-rate parallel circuit simulation

1. A computer implemented method of performing multi-rate circuit simulation in parallel, comprising:

partitioning the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations;

determining a simulation time step for each partition of the plurality of partitions;

grouping the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other; and

solving the multiple groups with their corresponding simulation time steps in parallel, comprising solving for boundary conditions between the fast group and the medium group, demoting a first partition from the medium group to the fast group in response to lack of convergence in solving for the first partition with the medium simulation time step, and promoting a second partition from the fast group to the medium group in response to convergence in solving for the second partition has been stable for a predetermined number of simulation cycles.

2. The computer implemented method of claim 1 , wherein the partitioning the circuit into a plurality of partitions comprises:

partitioning based at least in part on coupling between the plurality of partitions being smaller than a predetermined coupling strength.

3. The computer implemented method of claim 1 , wherein the determining a simulation time step for each partition of the plurality of partitions comprises:

discretizing the plurality of partitions and the corresponding sets of linear differential equations; and

for each set of differential equations, determining the simulation time step for solving the set of differential equations.

4. The computer implemented method of claim 1 , wherein the multiple groups comprises at least one of:

a fast group comprising one or more partitions having smallest simulation time steps among the plurality of partitions;

a slow group comprising one or more partitions having largest simulation time steps among the plurality of partitions; and

a medium group comprising one or more partitions having medium simulation time steps among the plurality of partitions.

5. The computer implemented method of claim 4 , wherein the medium group comprises:

one or more medium rate groups, wherein each of the one or more medium rate group comprises a different simulation time step.

6. The computer implemented method of claim 1 , wherein the grouping the plurality of partitions into multiple groups comprises:

for a group in the multiple groups,

creating the group to include one or more partitions having a common simulation time step; and

creating the group based on computational time of each partition in the group and computational parallelism of other partitions in the group.

7. The computer implemented method of claim 1 , wherein the solving for boundary conditions between the fast group and the medium group comprises:

solving for a new solution for a partition in the medium rate group using a previous solution for the partition in the medium rate group and a projected solution in the fast rate group.

8. The computer implemented method of claim 1 , wherein the solving the multiple groups with their corresponding simulation time steps in parallel further comprises:

solving for boundary conditions between the slow group and the medium group;

demoting a third partition from the slow group to the medium group in response to lack of convergence in solving for the third partition with the slow simulation time step; and

promoting a fourth partition from the medium group to the slow group in response to convergence in solving for the fourth partition has been stable for a predetermined number of simulation cycles.

9. The computer implemented method of claim 8 , wherein the solving for boundary conditions between the slow group and the medium group comprises:

solving for a new solution for a partition in the slow rate group using a previous solution for the partition in the slow rate group and a projected solution in the medium rate group.

10. An apparatus configured to perform multi-rate circuit simulation in parallel, comprising:

one or more processors;

a multi-rate circuit simulation module controlled by the one or more processors; wherein the multi-rate circuit simulation module comprises:

logic configured to partition the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations;

logic configured to determine a simulation time step for each partition of the plurality of partitions;

logic configured to group the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other; and

logic configured to solve the multiple groups with their corresponding simulation time steps in parallel, comprising logic configured to solve for boundary conditions between the fast group and the medium group, logic configured to demote a first partition from the medium group to the fast group in response to lack of convergence in solving for the first partition with the medium simulation time step, and logic configured to promote a second partition from the fast group to the medium group in response to convergence in solving for the second partition has been stable for a predetermined number of simulation cycles.

11. The apparatus of claim 10 , wherein the logic configured to partition the circuit into a plurality of partitions comprises:

logic configured to partition based at least in part on coupling between the plurality of partitions being smaller than a predetermined coupling strength.

12. The apparatus of claim 10 , wherein the logic configured to determine a simulation time step for each partition of the plurality of partitions comprises:

logic configured to discretize the plurality of partitions and the corresponding sets of linear differential equations; and

for each set of differential equations, logic configured to determine the simulation time step for solving the set of differential equations.

13. The apparatus of claim 10 , wherein the multiple groups comprises at least one of:

a fast group comprising one or more partitions having smallest simulation time steps among the plurality of partitions;

a slow group comprising one or more partitions having largest simulation time steps among the plurality of partitions; and

a medium group comprising one or more partitions having medium simulation time steps among the plurality of partitions.

14. The apparatus of claim 13 , wherein the medium group comprises:

one or more medium rate groups, wherein each of the one or more medium rate group comprises a different simulation time step.

15. The apparatus of claim 10 , wherein the logic configured to group the plurality of partitions into multiple groups comprises:

for a group in the multiple groups,

logic configured to create each group to include one or more partitions having a common simulation time step; and

logic configured to create the group based on computational time of each partition in the group and computational parallelism of other partitions in the group.

16. The apparatus of claim 10 , wherein the logic configured to solve for boundary conditions between the fast group and the medium group comprises:

logic configured to solve for a new solution for a partition in the medium rate group using a previous solution for the partition in the medium rate group and a projected solution in the fast rate group.

17. The apparatus of claim 10 , wherein the logic configured to solve the multiple groups with their corresponding simulation time steps in parallel further comprises:

logic configured to solve for boundary conditions between the slow group and the medium group;

logic configured to demote a third partition from the slow group to the medium group in response to lack of convergence in solving for the third partition with the slow simulation time step; and

logic configured to promote a fourth partition from the medium group to the slow group in response to convergence in solving for the fourth partition has been stable for a predetermined number of simulation cycles.

18. The apparatus of claim 17 , wherein the logic configured to solve for boundary conditions between the slow group and the medium group comprises:

logic configured to solve for a new solution for a partition in the slow rate group using a previous solution for the partition in the slow rate group and a projected solution in the medium rate group.

19. A system for performing multi-rate circuit simulation in parallel, comprising:

means for partitioning the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations;

means for determining a simulation time step for each partition of the plurality of partitions;

means for grouping the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other; and

means for solving the multiple groups with their corresponding simulation time steps in parallel, comprising means for solving for boundary conditions between the fast group and the medium group, means for demoting a first partition from the medium group to the fast group in response to lack of convergence in solving for the first partition with the medium simulation time step, and means for promoting a second partition from the fast group to the medium group in response to convergence in solving for the second partition has been stable for a predetermined number of simulation cycles.