IP Library Granted Patent US 9,780,169
Granted Patent B2
US 9,780,169 · App. 14/876,844 · Granted Oct 3, 2017

Semiconductor structure having epitaxial layers

Inventors: Chih-Kai Hsu (Tainan, TW); Yu-Hsiang Hung (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Yu-Cheng Tung (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW)
Assignee: UNTIED MICROELECTRONICS CORP.
H01L29/0847H01L27/0924H01L29/785
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Quick Facts
Patent No.
US 9,780,169
App. No.
14/876,844
Granted
Oct 3, 2017
Kind
B2
Abstract

The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.

Claims (18)

1. A semiconductor device, comprising:

a substrate, a first conductivity type region and a second conductivity type region being defined thereon;

a plurality of first fin structures disposed on the substrate and disposed within the first conductivity type region, a plurality of second fin structures disposed on the substrate and disposed within the second conductivity type region;

a plurality of first gate structures disposed within the first conductivity type region, across and over the first fin structures, and a plurality of second gate structures disposed within the second conductivity type region, across and over the second fin structures; and

at least two first crown epitaxial layers, disposed within the first conductivity type region and disposed on two sides of each first gate structure, and a plurality of second epitaxial layers, disposed within the second conductivity type region and disposed on two sides of each second gate structure, wherein the second epitaxial layer comprises a teeth epitaxial layer, and the teeth epitaxial layer has a top surface with a recessed and protruding profile, and wherein the first crown epitaxial layers are disposed in a first recess on two sides of the first gate structure, the first recess has a flat bottom surface, and each one first crown epitaxial layer contacts the plurality of first fin structures, wherein a top surface of each first crown epitaxial layer is higher than a top surface of each first fin structure, in addition, the shape of the second epitaxial layer is different from the shape of the first crown epitaxial layer.

2. The semiconductor device of claim 1 , wherein the first conductivity type region is a p-type transistor region, and the second conductivity type region is an n-type transistor region.

3. The semiconductor device of claim 1 , wherein the first conductivity type region is an n-type transistor region, and the second conductivity type region is a p-type transistor region.

4. The semiconductor device of claim 1 , wherein each first crown epitaxial layer has a flat bottom surface and a flat top surface.

5. The semiconductor device of claim 1 , wherein each first crown epitaxial layer is disposed on the sidewalls of a plurality of first fin structures, and the first crown epitaxial layer does not cover and is not disposed right above each first fin structure directly.

6. The semiconductor device of claim 1 , wherein the substrate at two sides of each second gate structure within the second region comprises a plurality of sub-fin structures, the sub-fin structures extend from the second fin structures, and a height of each sub-fin structure is smaller than a height of each second fin structure, and the teeth epitaxial layer directly covers and is disposed right above each sub-fin structure.

7. A semiconductor device, comprising:

a substrate, a first conductivity type region being defined thereon, the first conductivity type region including a first region and a second region;

a plurality of first fin structures disposed on the substrate and disposed within the first region, a plurality of second fin structures disposed on the substrate and disposed within the second region;

a plurality of first gate structures disposed within the first region, across and over the first fin structures, and a plurality of second gate structures disposed within the second region, across and over the second fin structures; and

at least two first crown epitaxial layers, disposed within the first region and disposed on two sides of each first gate structure, and a plurality of second epitaxial layers, disposed within the second region and disposed on two sides of each second gate structure, wherein the second epitaxial layer comprises a teeth epitaxial layer, and the teeth epitaxial layer has a top surface with a recessed and protruding profile, and wherein the first crown epitaxial layers are disposed in a first recess on two sides of the first gate structure, the first recess has a flat bottom surface, and each first crown epitaxial layer contacts the plurality of first fin structures, wherein a top surface of each first crown epitaxial layer is higher than a top surface of each first fin structure, in addition, the shape of the second epitaxial layer is different from the shape of the first crown epitaxial layer.

8. The semiconductor device of claim 7 , wherein the first conductivity type region is a p-type transistor region or an n-type transistor region.

9. The semiconductor device of claim 7 , wherein each first crown epitaxial layer has a flat bottom surface and a flat top surface.

10. The semiconductor device of claim 7 , wherein each first crown epitaxial layer is disposed on the sidewalls of a plurality of first fin structures, and the first crown epitaxial layer does not cover and is not disposed right above each first fin structure directly.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2015
From: HSU, CHIH-KAI; HUNG, YU-HSIANG; FU, SSU-I; TUNG, YU-CHENG; JENQ, JYH-SHYANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036741/0877 →
Priority Claims (1)
CN 2015 1 0577437 · Sep 11, 2015 · national
Continuity (1)
Related Publication 20170077229A1 · Mar 16, 2017