Gate driving circuit and display apparatus including the same
A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage.
1. A gate driving circuit comprising a plurality of stages for providing gate signals to gate lines of a display panel, a k-th stage of the stages comprising:
a first output transistor comprising a control electrode connected to a first node, an input electrode configured to receive a clock signal, and an output electrode configured to output a k-th gate signal;
a second output transistor comprising a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output a k-th carry signal;
a pull-down unit connected to a discharge node and configured to pull down the output electrode of the first output transistor in response to a signal of the discharge node; and
a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage,
wherein the discharge unit is further configured to output a (k+2)-th carry signal output from a (k+2)-th stage to the discharge node in response to a (k+3)-th carry signal output from a (k+3)-th stage.
2. The gate driving circuit of claim 1 , wherein the discharge unit comprises:
a first discharge transistor connected between the discharge node and the (k−1)-th carry signal, the first discharge transistor comprising a control electrode connected to the (k+1)-th carry signal; and
a second discharge transistor connected between the discharge node and the (k+2)-th carry signal, the second discharge transistor comprising a control electrode connected to the (k+3)-th carry signal.
3. The gate driving circuit of claim 2 , further comprising: a control unit configured to control potentials of the first node and a second node in response to a (k−3)-th carry signal output from a (k−3)-th stage, a (k+6)-th carry signal output from a (k+6)-th stage, and the (k+3)-th carry signal output from the (k+3)-th stage.
4. The gate driving circuit of claim 3 , wherein the pull-down unit comprises:
a first pull-down transistor connected between the output electrode of the first output transistor and a first ground voltage, the first pull-down transistor comprising a control electrode connected to the discharge node; and
a second pull-down transistor connected between the output electrode of the first output transistor and the first ground voltage, the second pull-down transistor comprising a control electrode connected to the second node.
5. The gate driving circuit of claim 1 , further comprising: a first capacitor connected between the output electrode of the first output transistor and the control electrode of the first output transistor; and a second capacitor connected between the output electrode of the second output transistor and the control electrode of the second output transistor.
6. The gate driving circuit of claim 5 , wherein a capacitance of the second capacitor is greater than that of the first capacitor.
7. A gate driving circuit comprising stages for providing gate signals to gate lines of a display panel, a k-th stage of the stages comprising:
a first output transistor comprising a control electrode connected to a first node, an input electrode configured to receive a clock signal, and an output electrode configured to output a k-th gate signal;
a second output transistor comprising a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output a k-th carry signal;
a pull-down unit connected to a discharge node and configured to pull down the output electrode of the first output transistor in response to a signal of the discharge node; and
a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+2)-th carry signal output from a (k+2)-th stage,
wherein the discharge unit is further configured to output a (k+3)-th carry signal output from a (k+3)-th stage to the discharge node in response to a (k+4)-th carry signal output from a (k+4)-th stage.
8. The gate driving circuit of claim 7 , wherein the discharge unit comprises:
a first discharge transistor connected between the discharge node and the (k−1)-th carry signal, the first discharge transistor comprising a control electrode connected to the (k+2)-th carry signal; and
a second discharge transistor connected between the discharge node and the (k+3)-th carry signal, the second discharge transistor comprising a control electrode connected to the (k+4)-th carry signal.
9. The gate driving circuit of claim 8 , further comprising: a control unit configured to control potentials of the first node and a second node in response to a (k−4)-th carry signal output from a (k−4)-th stage, a (k+8)-th carry signal output from a (k+8)-th stage, and the (k+4)-th carry signal output from the (k+4)-th stage.
10. The gate driving circuit of claim 9 , wherein the pull-down unit comprises:
a first pull-down transistor connected between the output electrode of the first output transistor and a first ground voltage, the first pull-down transistor comprising a control electrode connected to the discharge node; and
a second pull-down transistor connected between the output electrode of the first output transistor and the first ground voltage, the second pull-down transistor comprising a control electrode connected to the second node.
11. A display device comprising:
a display panel comprising a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines;
a data driving circuit configured to periodically invert a polarity of a data signal to drive the data lines; a gate driving circuit configured to output a plurality of gate signals for driving the gate lines in response to a clock signal; and
a driving control unit configured to provide the data signal to the data driving circuit and provide the clock signal to the gate driving circuit,
wherein the gate driving circuit comprises a plurality of stages, wherein a k-th stage of the stages comprises:
a first output transistor comprising a control electrode connected to a first node, an input electrode configured to receive the clock signal, and an output electrode configured to output a k-th gate signal;
a second output transistor comprising a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output a k-th carry signal;
a pull-down unit connected to a discharge node and configured to pull down the output electrode of the first output transistor in response to a signal of the discharge node; and
a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage,
wherein the discharge unit is further configured to output a (k+2)-th carry signal output from a (k+2)-th stage to the discharge node in response to a (k+3)-th carry signal output from a (k+3)-th stage.
12. The display device of claim 11 , wherein the discharge unit comprises: a first discharge transistor connected between the discharge node and the (k−1)-th carry signal, the first discharge transistor comprising a control electrode connected to the (k+1)-th carry signal; and a second discharge transistor connected between the discharge node and the (k+2)-th carry signal, the second discharge transistor comprising a control electrode connected to the (k+3)-th carry signal.
13. The display device of claim 12 , further comprising: a control unit configured to control potentials of the first node and a second node in response to a (k−3)-th carry signal output from a (k−3)-th stage, a (k+6)-th carry signal output from a (k+6)-th stage, and the (k+3)-th carry signal output from the (k+3)-th stage.
14. The display device of claim 13 , wherein the pull-down unit comprises:
a first pull-down transistor connected between the output electrode of the first output transistor and a first ground voltage, the first pull-down transistor comprising a control electrode connected to the discharge node; and
a second pull-down transistor connected between the output electrode of the first output transistor and the first ground voltage, the second pull-down transistor comprising a control electrode connected to the second node.
15. The display device of claim 11 , further comprising: a first capacitor connected between the output electrode of the first output transistor and the control electrode of the first output transistor; and a second capacitor connected between the output electrode of the second output transistor and the control electrode of the second output transistor.
16. The display device of claim 15 , wherein a capacitance of the second capacitor is greater than that of the first capacitor.