IP Library Granted Patent US 9,786,544
Granted Patent B2
US 9,786,544 · App. 14/456,870 · Granted Oct 10, 2017

Floating body memory cell apparatus and methods

Inventor: Paul Grisham (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76224H01L21/76232H01L21/76283H01L27/10802H01L27/10844H01L29/66795H01L29/7841
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Quick Facts
Patent No.
US 9,786,544
App. No.
14/456,870
Granted
Oct 10, 2017
Kind
B2
Abstract

Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described.

Claims (47)

1. A method comprising:

forming pillars from a first portion of a semiconductor material, each of the pillars including a first pillar portion and a second pillar portion, the second pillar portion being between the first pillar portion and a second portion of the semiconductor material;

removing the second pillar portion of each of the pillars after the pillars are formed to electrically isolate the first pillar portion of each of the pillars from the second portion of the semiconductor material; and

forming memory cells that include at least the first pillar portion of each of the pillars.

2. The method of claim 1 , wherein the second pillar portion of each of the pillars and the second portion of the semiconductor material include a same bulk silicon material.

3. The method of claim 1 , wherein forming the memory cells includes forming a source in the first pillar portion of the first pillar and forming a drain in the first pillar portion of the first pillar.

4. A method comprising:

forming pillars from a first portion of a semiconductor material, each of the pillars including a first pillar portion and a second pillar portion, the second pillar portion being between the first pillar portion and a second portion of the semiconductor material;

removing the second pillar portion of each of the pillars to electrically isolate the first pillar portion of each of the pillars from the second portion of the semiconductor material; and

forming memory cells that include at least the first pillar portion of each of the pillars, wherein forming the memory cells includes forming a first gate on a first side of the first pillar portion of a first pillar among the pillars and forming a second gate on a second side, opposite from the first side of the first pillar portion of the first pillar.

5. A method comprising:

forming pillars from a first portion of a semiconductor material, each of the pillars including a first pillar portion and a second pillar portion, the second pillar portion being between the first pillar portion and a second portion of the semiconductor material;

removing the second pillar portion of each of the pillars to electrically isolate the first pillar portion of each of the pillars from the second portion of the semiconductor material;

forming memory cells that include at least the first pillar portion of each of the pillars, wherein forming the memory cells includes forming a source in the first pillar portion of the first pillar and forming a drain in the first pillar portion of the first pillar; and

forming an insulation material between the source and the drain.

6. A method comprising:

forming isolation structures extending in a first direction in a first portion of a bulk silicon material;

forming trenches extending in a second direction in at least a part of the first portion of the bulk silicon material and in at least a part of the isolation structures to produce pillars in the first portion of the bulk silicon material, the pillars attached to and protruding from a second portion of the bulk silicon material;

removing a selected pillar portion of each of the pillars to electrically isolate a remaining pillar portion of each of the pillars from the second portion of the bulk silicon material; and

forming memory cells that include the remaining pillar portion of each of the pillars.

7. The method of claim 6 , wherein the isolation structures are formed with a first dimension in a third direction perpendicular to the first and second directions, and the trenches are formed with a second dimension in the third direction, such that the second dimension is less than the first dimension.

8. The method of claim 6 , further comprising:

filling an insulation material into a space resulting from the removing of the selected pillar portion of each of the pillars.

9. The method of claim 6 further comprising:

oxidizing at least a part of the remaining pillar portion each of the pillars after the selected pillar portion is removed and before the filling the insulation material into the space.

10. The method of claim 6 , wherein forming the memory cells includes forming a first region in each of the pillars to form a source of a memory cell and forming second region in each of the pillars to form a drain of a memory cell before the selected pillar portion of each of the pillars is removed.

11. The method of claim 10 , wherein forming the memory cells includes forming gates extending in the second direction.

12. A method comprising:

forming first isolation structures extending in a first direction in a first portion of a bulk silicon material;

forming second isolation structures extending in the first direction in the first portion of the bulk silicon material, such that each of the second isolation structures is between two of the first isolation structures and such that each of the first isolation structures is formed to a first depth the first portion of the bulk silicon material and each of the second isolation structures is formed to a second depth the first portion of the bulk silicon material, wherein the first depth is greater than the second depth;

forming trenches, extending in a second direction in the bulk silicon material perpendicular to the first and second isolation structures to produce pillars in the first portion of the bulk silicon material, the pillars attached to and protruding from a second portion of the bulk silicon material;

removing a selected pillar portion of each of the pillars to electrically isolate a remaining pillar portion of each of the pillars from the second portion of the bulk silicon material;

surrounding at least a part of the remaining pillar portion each of the pillars with an insulation material; and

forming memory cells that include the remaining pillar portion of each of the pillars.

13. The method of claim 12 , further comprising:

oxidizing an outer portion of the part of the remaining pillar portion each of the pillars before surrounding the part of the remaining pillar portion of each of the pillars with the insulation material.

14. The method of claim 13 , wherein surrounding at least the part of the remaining pillar portion of each of the pillars with the insulation material includes filling the insulation material into the trenches and into a space where the selected pillar portion of each of the pillars is removed.

15. The method of claim 12 , wherein removing the selected pillar portion of each of the pillars includes performing an etching process to remove the selected pillar portion of each of the pillars.

16. The method of claim 15 , wherein the etching process includes an isotropic etching process.

17. The method of claim 12 , wherein insulation material includes include an oxide of silicon.

18. The method of claim 12 , further comprising:

removing material from both sides in the second direction of the remaining pillar portion of each of the pillars.

19. The method of claim 18 , further comprising:

filling an additional insulation material into a space resulting from the removing of the material from both sides of the remaining pillar portion of each of the pillars.

20. The method of claim 19 , wherein forming the memory cells includes:

forming a first gate on a first side of the remaining pillar portion of each of the pillars; and

forming a second gate on a second side opposite from the first side of the remaining pillar portion of each of the pillars.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 12491923 · Jun 25, 2009
Related Publication 20140349457A1 · Nov 27, 2014