IP Library Granted Patent US 9,786,643
Granted Patent B2
US 9,786,643 · App. 14/325,619 · Granted Oct 10, 2017

Semiconductor devices comprising protected side surfaces and related methods

Inventors: Zhaohui Ma (Singapore, SG); Wei Zhou (Singapore, SG); Chee Chung So (Singapore, SG); Soo Loo Ang (Singapore, SG); Aibin Yu (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L25/18H01L21/561H01L21/563H01L21/6835H01L21/78H01L23/3107H01L23/3128H01L23/544H01L24/94H01L24/96H01L25/0657H01L25/50H01L2221/68359H01L2221/68381H01L2223/54433H01L2223/54486H01L2224/16145H01L2224/32145H01L2224/73204H01L2224/94H01L2224/97H01L2225/06513H01L2225/06541H01L2924/1431H01L2924/1434H01L2924/18161
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Quick Facts
Patent No.
US 9,786,643
App. No.
14/325,619
Granted
Oct 10, 2017
Kind
B2
Abstract

Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A protective material may be positioned between the die stacks and in the trenches, after which the wafer is thinned from a side opposite the die stacks to expose the protective material in the trenches. Semiconductor devices comprising stacks of dice and corresponding base semiconductor dice comprising wafer regions are separated from one another by cutting through the protective material along the streets and in the trenches. The protective material covers at least sides of each die stack as well as side surfaces of the corresponding base semiconductor die.

Claims (18)

1. A method, comprising:

forming trenches of a first width in streets between regions of a semiconductor wafer, each region sized and configured to bear a corresponding stack of semiconductor dice

positioning a stack of semiconductor dice on a surface of each region after forming the trenches in the streets, leaving a peripheral portion of the surface of each region exposed;

positioning a protective material only between the stacks of semiconductor dice, over the exposed peripheral portions of the regions, and in the trenches to leave bond pads located on the semiconductor die farthest from the semiconductor die of the stack proximate the semiconductor wafer exposed;

reducing a thickness of the semiconductor wafer from a back side of the semiconductor wafer to a final thickness to expose the protective material in the trenches at the back side surface of the semiconductor wafer;

connecting electrically conductive elements to at least some of the exposed bond pads located on a semiconductor die farthest from a semiconductor die of each stack proximate the semiconductor wafer; and

cutting between the regions of the semiconductor wafer and corresponding stacks of semiconductor dice by making cuts of a second, narrower width from the semiconductor dice of the stacks farthest from the semiconductor wafer completely through the protective material between the stacks of semiconductor devices and within the trenches, leaving the protective material on sides of the semiconductor dice of the die stacks and on side surfaces of the regions within the trenches; and

leaving the electrically conductive elements connected to the bond pads located on the semiconductor die farthest from the semiconductor die of the stack proximate the semiconductor wafer exposed for forming electrical connections between the stack of semiconductor dice to another device or structure.

2. The method of claim 1 , wherein forming the trenches comprises forming the trenches to a depth greater than or equal to the final thickness of the semiconductor wafer.

3. The method of claim 2 , wherein forming the trenches to the depth greater than or equal to the final thickness of the semiconductor wafer comprises forming the trenches to a depth greater than or equal to 40 microns.

4. The method of claim 1 , wherein forming the trenches comprises cutting partially through a thickness of the semiconductor wafer using a first blade configured to cut through material of the semiconductor wafer and cutting between the wafer regions and corresponding stacks of semiconductor dice comprises cutting completely through the protective material within the trenches using a second, different blade configured to cut through the protective material.

5. The method of claim 1 , wherein cutting between the wafer regions and stacks of semiconductor dice from one another comprises cutting through the protective material without cutting through material of the semiconductor wafer.

6. The method of claim 1 , wherein forming the trenches of the first width comprises forming the trenches to a first width between about one-tenth and about nine-tenths a third width of the streets.

7. The method of claim 6 , wherein forming the trenches to the first width between about one-tenth and about nine-tenths the third width of the streets comprises forming the trenches to a width between about 100 microns and about 200 microns.

8. The method of claim 1 , wherein positioning the protective material in the trenches comprises dispensing a flowable encapsulant material in the trenches and curing the encapsulant material.

9. The method of claim 1 , further comprising positioning a protective film over a backside of the semiconductor wafer before separating the wafer regions and corresponding stacks of semiconductor dice.

10. The method of claim 9 , wherein cutting through the wafer regions and corresponding stacks of semiconductor dice comprises cutting through the protective material and the protective film without cutting through material of the semiconductor wafer.

11. The method of claim 1 , wherein positioning the protective material between the stacks of semiconductor dice and in the trenches comprises positioning the protective material to one of a level substantially coincident with a height of the stacks of semiconductor dice and a level sufficient to extend over uppermost dice in the stacks of semiconductor dice.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2014
From: MA, ZHAOHUI; ZHOU, WEI; SO, CHEE CHUNG; ANG, SOO LOO; YU, AIBIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033260/0155 →
Continuity (1)
Related Publication 20160013154A1 · Jan 14, 2016