Electrostatic discharge device
An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.
1. An electrostatic discharge (ESD) device, comprising:
a power clamping circuit including a first Zener diode and a second Zener diode, a cathode of the first Zener diode being coupled to a first power supply line, an anode of the first Zener diode being coupled to an anode of the second Zener diode, and a cathode of the second Zener diode being coupled to a second power supply line; and
an isolation circuit including a first isolation diode and a second isolation diode, a cathode of the first isolation diode being coupled to the first power supply line, an anode of the first isolation diode being coupled to a cathode of the second isolation diode and a circuit being protected, and an anode of the second isolation diode being coupled to the second power supply line,
wherein at least one of first or second isolation diode includes
a P-type well formed in a substrate;
an N-type well formed in the P-type well; and
an N-type well formed in the P-type well in contact with a partial portion of the bottom of the first N-type region, having a, higher doping concentration than the first N-type well.
2. The ESD device of claim 1 , wherein the power clamping circuit includes:
a P-type well formed in a semiconductor substrate;
a first N-type region and a second N-type region formed in the P-type well, the first and second N-type regions sandwiching a portion of the P-type well, the first Zener diode including the first N-type region and the portion of the P-type well, and the second Zener diode including the second N-type region and the portion of the P-type well.
3. The ESD device of claim 2 , wherein the power clamping circuit further includes:
a first P-type region formed in the P-type well and below the first N-type region; and
a second P-type region formed in the P-type well and below the second N-type region,
the first and second N-type regions, the first and second P-type regions, and the P-type well forming a parasitic NPN bipolar-junction transistor structure.
4. The ESD protection device of claim 1 , wherein the N-type well is a first N-type well, at least one of the first or second isolation diode further including:
a second N-type well formed in the P-type well, the first and second N-type wells sandwiching a common P region in the P-type well; and
a heavily-doped P-type (P + ) region formed over the first N-type well and a heavily-doped N-type (N + ) region formed over the second N-type well.
5. The ESD protection device of claim 4 , wherein a distance between the first N-type well and the second N-type well is about 0.2 μm to about 5 μm.
6. The ESD protection device of claim 4 , wherein:
the N + region is a first N + region, and
the at least one of the first or second isolation diode further includes a second N + region formed in the P + region, the second N + region and the P + region being coupled to each other by a wiring.