Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes

1. A method of manufacturing a semiconductor device, the method comprising:

preparing a substrate having a plurality of active areas;

forming a plurality of bit line structures on the substrate and each comprising a bit line extending in a first direction and a bit line spacer layer extending along two opposing side surfaces of the bit line;

forming a plurality of contact holes spaced apart from one another along a lengthwise direction of a space between the plurality of bit line structures, and a plurality of first contact plugs filling bottom portions of the plurality of contact holes and electrically connected with the plurality of active areas;

forming a conductive material layer to fill the plurality of contact holes and to cover the plurality of bit line structures;

forming a plurality of first line patterns extending to form a diagonal line with respect to the first direction and arranged on the conductive material layer, and a plurality of second line patterns arranged on the plurality of first line patterns and crossing the plurality of first line patterns; and

forming a plurality of second contact plugs each electrically connected with respective ones of the plurality of first contact plugs, by etching the conductive material layer using the plurality of first line patterns and the plurality of second line patterns as an etch mask.

2. The method of claim 1 , wherein the plurality of first line patterns and the plurality of second line patterns form diagonal lines which extend at a same angle with respect to the first direction.

3. The method of claim 1 , wherein each of the plurality of active areas has a major axis extending along a direction of the diagonal line with respect to the first direction.

4. The method of claim 3 , wherein the major axis of each of the plurality of active areas has a first angle with respect to the first direction, and

the plurality of first line patterns and the plurality of second line patterns extend by a second angle and a third angle, respectively, with respect to the first direction, wherein the first angle is greater than 0° and less than the second angle and the third angle.

5. The method of claim 1 , wherein portions of the plurality of first line patterns, crossed by the plurality of second line patterns, are arranged as a hexagonal array structure with respect to a main surface of the substrate.

6. The method of claim 1 , wherein portions of the plurality of first line patterns, crossed by the plurality of second line patterns, have a diamond shaped cross-sectional plane.

7. The method of claim 1 , wherein portions of the plurality of first line patterns, crossed by the plurality of second line patterns, overlap portions of the plurality of bit line structures and portions of the plurality of contact holes in a direction perpendicular to a main surface of the substrate.

8. The method of claim 1 , wherein at least a portion of a space in which a first space which is a space between the plurality of first line patterns and a second space which is a space between the plurality of second line patterns cross each other overlaps the plurality of first contact plugs in a direction perpendicular to a main surface of the substrate.

9. The method of claim 1 , wherein the forming of the plurality of second contact plugs comprises etching the conductive material layer until the plurality of second line patterns are completely removed and at least some portions of the plurality of first line patterns, crossed by the plurality of second line patterns, remain.

10. The method of claim 1 , wherein the forming of the plurality of second contact plugs comprises etching the conductive material layer until portions of the plurality of first line patterns, not crossed by the plurality of second line patterns, are completely removed, and portions of the conductive material layer on upper surfaces of the plurality of bit line structures, are completely removed.

11. The method of claim 1 , wherein the plurality of first line patterns have a first pitch and are obtained by a double patterning process with respect to a mother pattern which is formed by a photolithography process to have a pitch that is at least twice the first pitch.

12. The method of claim 11 , wherein the plurality of second line patterns have a second pitch and are obtained by a double patterning process with respect to a mother pattern which is formed by a photolithography process to have a pitch that is at least twice the second pitch.