Power gate switching system
A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.
1. A semiconductor device, comprising:
a virtual power line extended in a first direction;
an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row;
a first power gate cell disposed in the n-well;
a second power gate cell disposed in the n-well, wherein the first and second power gate cells are first type cells; and
a third power gate cell disposed in the n-well between the first and second power gate cells, wherein the third power gate cell is a second type cell different from the first type cells.
2. The semiconductor device of claim 1 , wherein the third power gate cell is disposed closer to the first power gate cell than the second power gate cell.
3. The semiconductor device of claim 1 , wherein the third power gate cell is disposed closer to the second power gate cell than the first power gate cell.
4. The semiconductor device of claim 1 , wherein the each of the first type cells includes a gate electrode disposed between a pair of diffusion regions and a tab disposed adjacent to one of the diffusion regions.
5. The semiconductor device of claim 4 , wherein the tab is a p-tab, and in a row adjacent to the row of the n-well, an n-tab is disposed on the same axis with the p-tab, and the n-tab is connected to a ground line.
6. The semiconductor device of claim 4 , wherein the second type cell includes a gate electrode disposed between a pair of diffusion regions, and wherein the second type cell does not include a tab.
7. The semiconductor device of claim 1 , wherein the size of the second type cell is smaller than a size of each of the first type cells.
8. The semiconductor device of claim 1 , wherein the n-well is disposed in a p-type substrate.
9. The semiconductor device of claim 1 , wherein the n-well is doped with n-type impurities.
10. The semiconductor device of claim 1 , wherein the first power gate cell includes a gate electrode disposed between first and second diffusion regions, and a first tab disposed adjacent to the first or second diffusion region.
11. The semiconductor device of claim 10 , wherein the first and second diffusion regions are doped with p-type impurities and the first tab is doped with an n-type impurity.
12. The semiconductor device of claim 10 , wherein the first tab is connected to the virtual power line, the first diffusion region is connected to a real power line and the second diffusion region is connected to the virtual power line.
13. The semiconductor device of claim 12 , wherein the third power gate cell includes a gate electrode disposed between third and fourth diffusion regions, and wherein the second type cell does not include a tab, and wherein the third diffusion region is connected to the real power line and the fourth diffusion region is connected to the virtual power line.
14. A power gate switching system, comprising:
a first virtual power line extended in a first direction;
a first power gate cell connected to the first virtual power line;
a second power gate cell connected to the first virtual power line, wherein the first and second power gate cells each include at least one tab; and
a third power gate cell connected to the first virtual power line and disposed between the first and second power gate cells, wherein the third power gate cell does not include a tab, and
wherein the first to third power gate cells and the first virtual power line are arranged in a first row.
15. The power gate switching system of claim 14 , wherein the first row includes a plurality of logic cells disposed between the first power gate cell and the third power gate cell and a plurality of logic cells disposed between the second power gate cell and the third power gate cell.
16. The power gate switching system of claim 14 , wherein the first power gate cell includes a gate electrode disposed between first and second diffusion regions.
17. The power gate switching system of claim 16 , wherein the at least one tab of the first power gate cell is disposed adjacent to the first or second diffusion region.