IP Library Granted Patent US 9,786,769
Granted Patent B2
US 9,786,769 · App. 15/036,058 · Granted Oct 10, 2017

Complementary tunneling FET devices and method for forming the same

Inventor: Aleksandar Aleksov (Chandler, AZ)
Assignee: Intel Corporation
H01L29/66977H01L29/068H01L29/24H01L29/267H01L29/4238H01L29/42364H01L29/42376H01L29/7391H01L29/7869H01L51/0036H01L51/0037H01L51/0038H01L51/0078H01L51/0533H01L51/0554H01L51/0562H01L21/8258H01L29/0673H01L29/42392H01L29/785H01L29/7851
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Quick Facts
Patent No.
US 9,786,769
App. No.
15/036,058
Granted
Oct 10, 2017
Kind
B2
Abstract

Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.

Claims (10)

1. A tunneling field effect transistor (TFET), comprising:

a substrate;

a doped first region, disposed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table;

a doped second region, disposed above the substrate, having transparent or semi-transparent oxide n-type semiconductor material; and

a gate stack coupled to the doped first and second regions.

2. The TFET of claim 1 , wherein the transparent or semi-transparent oxide n-type semiconductor material is selected from a group consisting of α-Ga 2 —O 3 , β-Ga 2 —O 3 , In 2 O 3 , and SnO 2 .

3. The TFET of claim 1 , wherein the TFET is a FinFET, Tri-Gate, or square nano-wire based device.

4. The TFET of claim 1 further comprises a lightly doped n-type material coupled to the gate stack, the lightly doped n-type material separating the first and second doped regions from one another.

5. The TFET of claim 1 further comprises a lightly doped p-type material coupled to the gate stack, the lightly doped p-type material separating the first and second doped regions from one another.

6. The TFET of claim 1 , wherein the doped first region is a source region, and wherein the doped second region is a drain region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2016
From: ALEKSOV, ALEKSANDAR
To: INTEL CORPORATION
Reel/Frame 038652/0117 →
Continuity (1)
Related Publication 20160268401A1 · Sep 15, 2016