IP Library › Granted Patent US 9,786,856
Granted Patent B2
US 9,786,856 · App. 15/237,447 · Granted Oct 10, 2017

Method of manufacturing an image sensor device

Inventors: Shawn Michael O'Rourke (Colorado Springs, CO); Byung-Kyu Park (Colorado Springs, CO); Robert Rodriquez (Colorado Springs, CO)
Assignee: dpiX, LLC
H01L51/4253H01L27/1446H01L27/307H01L51/0004H01L51/0022H01L51/441H01L51/442H01L51/448Y02E10/549
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Quick Facts
Patent No.
US 9,786,856
App. No.
15/237,447
Granted
Oct 10, 2017
Kind
B2
Abstract

A method of manufacturing an image sensor device includes providing a metalized thin film transistor layer on a glass substrate; forming an inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the inter-layer dielectric layer; forming a metal layer the inter-layer dielectric and within the inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a bank layer on the metal layer and the inter-layer dielectric layer; forming a via through the bank layer; forming an electron transport layer on the bank layer and within the bank layer via for contacting an upper surface of the metal layer; forming a bulk heterojunction layer on the electron transport layer; forming a hole transport layer on the bulk heterojunction layer; and forming a top contact layer on the hole transport layer.

Claims (41)

1. A method of manufacturing an image sensor device comprising:

providing a metalized thin film transistor layer form on a glass substrate;

forming a first inter-layer dielectric layer on the metalized thin film transistor layer;

forming a via through the first inter-layer dielectric layer;

forming a metal layer on an upper surface of the first inter-layer dielectric and within the first inter-layer dielectric layer via for contacting the metalized thin film transistor layer;

forming a second inter-layer dielectric layer on an upper surface of the metal layer and the first inter-layer dielectric layer;

forming a via through the second inter-layer dielectric layer;

forming a conductive oxide layer on an upper surface of the second inter-layer dielectric layer and within the second inter-layer dielectric layer via for contacting an upper surface of the metal layer;

forming an electron transport layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer;

forming a bulk heterojunction layer on an upper surface of the electron transport layer;

forming a hole transport layer on an upper surface of the bulk heterojunction layer; and

forming a top contact layer on an upper surface of the hole transport layer.

2. The method of claim 1 , wherein the first and second inter-layer dielectric layers each comprise a SiON, Si 02 , or SiN layer.

3. The method of claim 1 , wherein the metal layer comprises a quad-layer metal stack layer.

4. The method of claim 1 , wherein the conductive oxide layer comprises an ITO, IGZO, IZO, ITZO, or AZO layer.

5. The method of claim 1 , wherein the electron transport layer comprises a work function tuning layer.

6. The method of claim 1 , wherein the bulk heterojunction layer comprises a photoactive layer.

7. The method of claim 1 , wherein the hole transport layer comprises a work function tuning layer.

8. The method of claim 1 , wherein the top contact layer comprises an anode layer.

9. A method of manufacturing an image sensor device comprising:

providing a metalized thin film transistor layer form on a glass substrate;

forming a first inter-layer dielectric layer on the metalized thin film transistor layer;

forming a via through the first inter-layer dielectric layer;

forming a metal layer on an upper surface of the first inter-layer dielectric and within the first inter-layer dielectric layer via for contacting the metalized thin film transistor layer;

forming a second inter-layer dielectric layer on an upper surface of the metal layer and the first inter-layer dielectric layer;

forming a via through the second inter-layer dielectric layer;

forming a conductive oxide layer on an upper surface of the second inter-layer dielectric layer and within the second inter-layer dielectric layer via for contacting an upper surface of the metal layer:

forming a bank layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer;

forming a via through the bank layer;

forming an electron transport layer on an upper surface of the bank layer and within the bank layer via to contact an upper surface of the conductive oxide layer;

forming a bulk heterojunction layer on an upper surface of the electron transport layer:

forming a hole transport layer on an upper surface of the bulk heterojunction layer; and

forming a top contact layer on an upper surface of the hole transport layer.

10. The method of claim 9 , wherein the first and second inter-layer dielectric layers each comprise a SiON, Si 02 , or SiN layer.

11. The method of claim 9 , wherein the metal layer comprises a quad-layer metal stack layer.

12. The method of claim 9 , wherein the conductive oxide layer comprises an ITO, IGZO, IZO, ITZO, or AZO layer.

13. The method of claim 9 , wherein the bank layer comprises a resin layer.

14. The method of claim 9 , wherein the electron transport layer comprises a work function tuning layer.

15. The method of claim 9 , wherein the bulk heterojunction layer comprises a photoactive layer.

16. The method of claim 9 , wherein the hole transport layer comprises a work function tuning layer.

17. The method of claim 9 , wherein the top contact layer comprises an anode layer.

Continuity (3)
Provisional Application 62283091 · Aug 20, 2015
Provisional Application 62283881 · Sep 14, 2015
Related Publication 20170054097A1 · Feb 23, 2017