Method and apparatus for automatic relative placement generation for clock trees

1. A method of circuit design executed by a computer implemented place and route tool, comprising:

processing a net list using the tool to determine relative placement groups identified by the relative placement information in the netlist, and to determine clock tree sinks in the netlist;

performing clock tree synthesis using the tool to add one or more elements to the input netlist from a group of elements including buffers, integrated clock gating, and clock drivers, to clock network flip-flops coupled to the clock tree sinks in clock clusters, and allocating the clock network flip-flops and added elements in the clock clusters to relative placement groups;

performing an initial placement using the tool to specify physical locations of the relative placement groups, including relative placement groups to which the clock network flip-flops and added elements in the clock clusters have been allocated; and

performing an incremental placement using the tool based on the specified physical locations of the relative placement groups determined by the initial placement.

2. The method of claim 1 , further including:

adding the clock network flip-flops to the netlist before performing the clock tree synthesis.

3. The method of claim 1 , wherein

the allocating of the clock network flip-flops and added elements to relative placement groups, includes changing a preexisting relative placement group.

4. The method of claim 1 , wherein the clock network flip-flops are leaf nodes of a clock tree of the circuit design.

5. The method of claim 1 , including performing a first placement using the first relative placement groups determined before said performing clock tree synthesis, and using information from the first placement in the clock tree synthesis.

6. A computer program product including a tangible non-transitory computer readable medium with computer readable instructions executable by a computer system, the computer readable instructions comprising:

instructions processing a net list to determine relative placement groups and clock tree sinks;

instructions performing clock tree synthesis to add one or more elements to the input netlist from a group of elements including buffers, integrated clock gating, and clock drivers, to clock network flip-flops coupled to the clock tree sinks in clock clusters, and allocating the clock network flip-flops and added elements in the clock clusters to the relative placement groups;

instructions performing an initial placement to specify physical locations of the relative placement groups, including relative placement groups to which the clock network flip-flops and added elements in the clock clusters have been allocated; and

instructions performing an incremental placement using the physical locations of the relative placement groups determined by the initial placement.

7. The computer program product of claim 6 , further including:

instructions adding clock network flip-flops to the netlist before performing the clock tree synthesis.

8. The computer program product of claim 6 , further including:

the instructions allocating of the clock network flip-flops and added elements to relative placement groups, changing a preexisting relative placement group.

9. The computer program product of claim 6 , wherein the clock network flip-flops are leaf nodes of a clock tree of the circuit design.

10. The computer program product of claim 6 , including instructions performing a first placement using relative placement groups determined before said performing clock tree synthesis, and using information from the first placement in the clock tree synthesis.