Fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer

1. A semiconductor device, the device comprising:

one or more fins formed on a substrate and extending along a first direction;

one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including a first isolation gate and a functional gate;

a first sidewall spacer disposed along the first isolation gate; and

source/drain features formed on two sides of each of the one or more gates;

wherein a first height of the first isolation gate is greater than a second height of the functional gate,

wherein the first isolation gate includes a dielectric layer and a metal gate layer, the first isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, one of the source/drain features, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a first depth and the one of the source/drain features extending into the substrate to a second depth, the first depth being greater than the second depth.

2. The device of claim 1 , wherein the dielectric layer includes a high k (HK) dielectric layer, and

wherein the metal gate layer is disposed over the HK dielectric layer.

3. The device of claim 1 , wherein the dielectric layer includes one or more dielectric materials selected from the group consisting of SiO2, LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), HfO 2 , BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 , Si 3 N 4 , and silicon oxynitride (SiON).

4. The device of claim 1 , further comprising one or more isolation regions formed on the substrate, wherein the one or more fins are separated by the one or more isolation regions.

5. The device of claim 1 , wherein the one or more fins include a first group of fins formed in a first doped region, and a second group of fins formed in a second doped region.

6. The device of claim 1 , wherein the first sidewall spacer includes a first material different from the dielectric layer of the first isolation gate.

7. The device of claim 1 , further comprising:

a second isolation gate formed at an edge of the one or more fins;

a second sidewall spacer formed on an outside edge of the second isolation gate; and

a third sidewall spacer formed on an inside edge of the second isolation gate,

wherein a height of the second sidewall spacer is greater than a height of the third sidewall spacer.

8. A fin-like field-effect transistor (FinFET) device, the device comprising:

a substrate including a first active region and a second active region spaced apart from each other in a first direction;

a first group of fins configured in the first active region, and a second group of fins configured in the second active region, each of the first group of fins and the second group of fins extending along a second direction substantially perpendicular to the first direction;

one or more gates configured to extend over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and a functional gate;

a first sidewall spacer disposed along the first isolation gate;

a source/drain feature formed on a side of the first sidewall spacer and extending into the substrate to a first depth; and

wherein a first height of the first isolation gate is greater than a second height of the first sidewall spacer of the first isolation gate,

wherein the first isolation gate includes a dielectric layer and a metal gate layer, the first isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, the source/drain feature, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a second depth that is greater than the first depth.

9. The device of claim 8 , wherein the first height of the first isolation gate is greater than a third height of each of the functional gate.

10. The device of claim 8 , further comprising:

a second isolation gate formed at an edge of the one or more fins;

a second sidewall spacer formed on an outside edge of the second isolation gate; and

a third sidewall spacer formed on an inside edge of the second isolation gate,

wherein an outside portion of the second isolation gate and the second sidewall spacer have a fourth height,

wherein an inside portion of the second isolation gate and the third sidewall spacer have a fifth height, and

wherein the fourth height is greater than the fifth height.

11. The device of claim 8 , wherein the first isolation gate includes a first material, and the functional gate includes a second material different from the first material.

12. The device of claim 8 , further comprising a second isolation gate comprising a second metal gate electrode extending into the substrate to a second depth, and

wherein the first isolation gate includes a first metal gate electrode extending into the substrate to a first depth, and

wherein the first depth is greater than the second depth.

13. The device of claim 8 , wherein the dielectric layer extends into the substrate to a first depth in the substrate, and

wherein the source/drain feature extends into the substrate to a second depth that is less than first depth.

14. A semiconductor device, comprising:

a substrate including a first active region and a second active region spaced apart from each other in a first direction;

a first group of fins configured in the first active region, and a second group of fins configured in the second active region, each of the first group of fins and the second group of fins extending along a second direction substantially perpendicular to the first direction; and

one or more gates configured to extend over the first active region and the second active region, each of the one or more gates extending along the first direction, the one or more gates including an isolation gate and a functional gate;

a first sidewall spacer disposed along the isolation gate;

a first source/drain feature formed on a side of the first sidewall spacer and extending into the substrate to a first depth; and

wherein the isolation gate includes a dielectric layer and a metal gate layer, the isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, the first source/drain feature, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a second depth that is greater than the first depth.

15. The device of claim 14 , further comprising:

a second source/drain feature disposed in the substrate, and

wherein the dielectric layer physically contacts the second source/drain feature.

16. The device of claim 14 , further comprising:

a second sidewall spacer disposed along a second isolation gate,

wherein the second sidewall spacer has a greater height than the first sidewall spacer.

17. The device of claim 14 , wherein the metal gate layer is disposed over the dielectric layer.

18. The device of claim 14 , wherein the dielectric layer is formed of a different material than the first sidewall spacer.

19. The device of claim 14 , wherein the dielectric layer includes a high-k (HK) dielectric layer.

20. The device of claim 14 , further comprising a second sidewall spacer disposed along the function gate, and

wherein the first source/drain feature extends from the first sidewall spacer to the second sidewall spacer.