Semiconductor lateral sidewall growth from a semiconductor pillar
A method is provided that may include providing a plurality of semiconductor pillars extending from a surface of a substrate, wherein a spacer is present on sidewall surfaces of each semiconductor pillar. A seed hole is then formed in a portion of each spacer that exposes a portion of at least one sidewall surface of each semiconductor pillar. Next, a semiconductor nanowire is epitaxially grown from the exposed portion of the at least one sidewall surface of each semiconductor pillar and entirely through each seed hole. A gate structure is then formed straddling over a channel portion of each semiconductor nanowire.
1. A method of forming a semiconductor structure, said method comprising:
providing a plurality of semiconductor pillars extending from a surface of a substrate, wherein a spacer is present on sidewall surfaces of each semiconductor pillar;
forming a seed hole in a portion of each spacer that exposes a portion of at least one sidewall surface of each semiconductor pillar;
epitaxially growing a semiconductor nanowire from said exposed portion of said at least one sidewall surface of each semiconductor pillar and entirely through each seed hole; and
forming a gate structure straddling over a channel portion of each semiconductor nanowire.
2. The method of claim 1 , wherein said gate structure is a sacrificial gate structure, and said method further comprises:
forming a source/drain structure on each side of said sacrificial gate structure;
removing a portion of each semiconductor pillar; and
replacing said sacrificial gate structure with a functional gate structure.
3. The method of claim 2 , wherein said forming said source/drain structure comprises:
forming a doped semiconductor material on a portion of each semiconductor nanowire not protected by said sacrificial gate structure; and
diffusing dopants from said doped semiconductor material into said portion of semiconductor nanowire not protected by said sacrificial gate structure.
4. The method of claim 1 , further comprising forming a local isolation region in a gap located between each semiconductor pillar.
5. The method of claim 1 , wherein said forming said seed hole comprises:
providing a patterned resist having openings formed therein, said openings are located over at least a portion of each semiconductor pillar; and
performing a wet etch to provide said seed hole in said spacer.
6. The method of claim 5 , wherein a sacrificial material is formed within each opening to shrink a width of each opening.
7. The method of claim 2 , further comprising forming a middle-of-the-line (MOL) dielectric material after removing said portion of each semiconductor pillar and said replacing said sacrificial gate structure with said functional gate structure.
8. The method of claim 7 , wherein, after replacing said sacrificial gate structure with said functional gate structure contact structure, contact structure are formed into said MOL dielectric material.
9. The method of claim 1 , wherein said gate structure is a functional gate structure, and said method further comprises:
forming a source/drain structure on each side of said functional gate structure; and
removing a portion of each semiconductor pillar.
10. The method of claim 9 , wherein said forming said source/drain structure comprises:
forming a doped semiconductor material on a portion of each semiconductor nanowire not protected by said functional gate structure; and
diffusing dopants from said doped semiconductor material into said portion of semiconductor nanowire not protected by said functional gate structure.
11. A semiconductor structure comprising:
a plurality of semiconductor nanowires oriented parallel to each other, wherein one end of each of said semiconductor nanowires is present in a seed hole provided in a first spacer, and another end of each of said semiconductor nanowires contacts a sidewall surface of a second spacer; and
a functional gate structure oriented perpendicular to and straddling over a channel portion of each of said semiconductor nanowires.
12. The semiconductor structure of claim 11 , wherein each semiconductor nanowire of said plurality of semiconductor nanowire is located on a surface of a local isolation region.
13. The semiconductor structure of claim 12 , wherein each local isolation region is spaced apart by a mesa portion of a semiconductor material.
14. The semiconductor structure of claim 13 , wherein said mesa portion of said semiconductor material is an extension of a semiconductor material layer.
15. The semiconductor structure of claim 11 , wherein each semiconductor nanowire comprises a III-V compound semiconductor.
16. The semiconductor structure of claim 11 , further comprising a source/drain structure located on each side of said functional gate structure.
17. The semiconductor structure of claim 16 , wherein each source/drain structure comprises an upper portion composed of a doped semiconductor material, and a lower portion composed of a doped portion of each of said semiconductor nanowires.
18. The semiconductor structure of claim 17 , wherein said lower portion of said source/drain structure is located adjacent said channel region of said semiconductor nanowires.
19. The semiconductor structure of claim 17 , further comprising a middle-of the-line (MOL) dielectric material surrounding each semiconductor nanowire and having a topmost surface that is coplanar with a topmost surface of said functional gate structure.
20. The semiconductor structure of claim 18 , further comprising contact structures located within said MOL dielectric material, wherein one of said contact structures contacts a sidewall of said upper portion and said lower portion of one of said source/drain structures.