Integrated circuit
An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.
1. An integrated circuit comprising:
a phase detector configured to generate a delay control signal by comparing the phases of first and second clock signals to first and second target positions;
a variable delay unit configured to shift the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal; and
a position controller configured to vary the first and second target positions according to an operation mode,
wherein the operation mode comprises a first and second operation modes,
during the first operation mode, the first target position corresponds to the center of the data and the second target position corresponds to an edge of the data, and
during the second operation mode, the first target position corresponds to the edge of the data and the second target position corresponds to the center of the data.
2. The integrated circuit of claim 1 , wherein the phase detector comprises:
an alignment unit configured to align data in response to the first and second clock signals;
a first decoding unit configured to generate a first control signal by decoding the data aligned by the alignment unit;
a second decoding unit configured to generate a second control signal by decoding the data aligned by the alignment unit; and
a multiplexing unit configured to output the first or second control signal as the delay control signal according to the operation mode.
3. The integrated circuit of claim 2 , further comprising an output unit configured to output any one of the data aligned by the alignment unit as recovery data according to the operation mode.
4. An integrated circuit comprising:
a delay unit configured to delay input data by a predetermined time;
a reset signal generator configured to generate a reset signal in response to the input data and an output signal of the delay unit;
an oscillator configured to generate first and second clock signals in response to the reset signal;
a phase detector configured to generate a delay control signal by comparing the phases of the first and second clock signals to first and second target positions corresponding to the respective phases;
a variable delay unit configured to delay the first clock signal to the first target position and delay the second clock signal to the second target position, in response to the delay control signal; and
a position controller configured to change the first and second target positions according to an operation mode,
wherein the phase detector comprises:
an alignment unit configured to align data in response to the first and second clock signals;
a first decoding unit configured to generate a first control signal by decoding the data aligned by the alignment unit;
a second decoding unit configured to generate a second control signal by decoding the data aligned by the alignment unit; and
a multiplexing unit configured to output the first or second control signal as the delay control signal according to the operation mode.
5. The integrated circuit of claim 4 , wherein the operation mode comprises first and second operation modes,
during the first operation mode, the first target position corresponds to the center of the data and the second target position corresponds to an edge of the data, and
during the second operation mode, the first target position corresponds to the edge of the data and the second target position corresponds to the center of the data.
6. The integrated circuit of claim 4 , further comprising an output unit configured to output any one of the data aligned by the alignment unit as recovery data according to the operation mode.
7. The integrated circuit of claim 4 , wherein the operation mode has information corresponding to the frequency at which the data are inputted.
8. An operating method of a clock data recovery circuit, comprising:
selecting an operation mode according to the frequency of data;
setting a first target position and a second target position of first and second clock signals in response to the operation mode, and performing a phase comparison according to the target positions;
adjusting frequencies and delay s of the first and second clock signals according to the result of the performing of the phase comparison; and
recovering the data in response to the first and second clock signals,
wherein the performing of the phase comparison comprises:
aligning the data in response to the first and second clock signals;
generating first and second control signals by decoding the aligned data; and
outputting the first or second control signal as a delay control signal for adjusting the frequencies and delay s of the first and second signals, according to the operation mode.
9. The operating method of claim 8 , wherein the recovering of the data comprises:
outputting first data synchronized with the first clock signal as recovery data according to the operation mode; and
outputting second data synchronized with the second clock signal as the recovery data according to the operation mode.
10. The operating method of claim 8 , wherein the operation mode comprises a first and second operation mode,
during the first operation mode, the first target position corresponds to the center of the data and the second target position corresponds to an edge of the data, and
during the second operation mode, the first target position corresponds to the edge of the data and the second target position corresponds to the center of the data.