IP Library › Granted Patent US 9,799,648
Granted Patent B2
US 9,799,648 · App. 14/990,092 · Granted Oct 24, 2017

Semiconductor device

Inventors: Atsushi Narazaki (Tokyo, JP); Shinya Soneda (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L27/0755H01L29/0619H01L29/41741H01L29/7397H01L29/8613H01L29/0692H01L29/0696
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Quick Facts
Patent No.
US 9,799,648
App. No.
14/990,092
Granted
Oct 24, 2017
Kind
B2
Abstract

A semiconductor device of the present invention includes: an IGBT including an emitter layer on a first main surface side of a semiconductor substrate and a collector layer on a second main surface side of the semiconductor substrate; a freewheeling diode including an anode layer on the first main surface side of the semiconductor substrate and a cathode layer on the second main surface side of the semiconductor substrate; a well region that is located in a boundary between the IGBT and the freewheeling diode and separates the IGBT and the freewheeling diode; a first electrode located on the first main surface of the semiconductor substrate so as to be connected to the emitter layer, the anode layer, and the well region; a resistance element located between the well region and the first electrode.

Claims (24)

1. A semiconductor device, comprising:

an insulated gate bipolar transistor including an emitter layer on a first main surface side of a semiconductor substrate and a collector layer on a second main surface side of said semiconductor substrate;

a freewheeling diode including an anode layer on said first main surface side of said semiconductor substrate and a cathode layer on said second main surface side of said semiconductor substrate;

a well region that is located in a boundary between said insulated gate bipolar transistor and said freewheeling diode and separates said insulated gate bipolar transistor and said freewheeling diode;

a first electrode located on said first main surface of said semiconductor substrate so as to be connected to said emitter layer, said anode layer, and said well region;

a resistance element located only between said well region and said first electrode;

a second electrode located on said second main surface of said semiconductor substrate so as to be connected to said collector layer and said cathode layer; and

an insulating film located between said first electrode and said well region including at least one opening, wherein

said resistance element is located in said opening, and

said first electrode and said well region are electrically connected through said resistance element.

2. The semiconductor device according to claim 1 , wherein said well region overlaps said collector layer so as to be included in said collector layer in plan view.

3. The semiconductor device according to claim 1 , further comprising a termination region located on said semiconductor substrate so as to surround said insulated gate bipolar transistor and said freewheeling diode in plan view, wherein

said first electrode is also connected to said termination region, and

said resistance element is also located between said termination region and said first electrode.

4. The semiconductor device according to claim 1 , wherein

said at least one opening includes a plurality of openings,

said well region and said first electrode are connected to each other through said plurality of openings separated from each other, and

said resistance element is located in each of said plurality of openings.

5. The semiconductor device according to claim 1 , wherein said resistance element comprises polysilicon.

6. The semiconductor device according to claim 1 , wherein said resistance element comprises titanium.

7. The semiconductor device according to claim 1 , wherein said resistance element comprises cobalt.

8. The semiconductor device according to claim 1 , wherein said insulated gate bipolar transistor comprises an injection enhanced type.

9. The semiconductor device according to claim 1 , wherein

the boundary is directly above a junction of the collector layer and the cathode layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2016
From: NARAZAKI, ATSUSHI; SONEDA, SHINYA
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 037430/0416 →
Priority Claims (1)
JP 2015-077490 · Apr 6, 2015 · national
Continuity (1)
Related Publication 20160293595A1 · Oct 6, 2016