Configurable vertical integration
The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.
1. A method of information processing using a stacked integrated circuit comprising a network comprising a plurality of control circuit portions, including redundant control circuit portions, a plurality of information bus circuit portions, and a plurality of processing circuit portions, wherein for purposes of redundancy there are a plurality of separate or partially separate interconnection paths interconnecting at least two control circuit portions of the plurality of control circuit portions, the method comprising: establishing a control network using at least one of the plurality of separate or partially separate interconnection paths the control network configuring or enabling or disabling the operation of one or more information processing circuit portions and one or more bus circuit portions; and performing information processing between at least two of the processing circuit portions.
2. A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of control circuit portions, including redundant control circuit portions, wherein there are a plurality of separate or partially separate, redundant interconnection paths interconnecting at least two control circuit portions of the plurality of control circuit portions, and a plurality of circuit portions comprising at least one of a bus circuit portion and a processing circuit portion, the method comprising: i. establishing a control network using at least one of the plurality of separate or partially separate, redundant interconnection paths; ii. disabling the plurality of circuit portions; iii selecting for testing at one time at least one of the plurality of circuit portions, iv. using the control network to enable for testing the selected at least one of the plurality of circuit portions, v. testing the selected at least one of the plurality of circuit portions; vi. using the control network to disable the selected at least one of the plurality of circuit portions if it failed testing, and vii. repeating steps ii. through vi. until a majority or all of the plurality of circuit portions have been tested.
3. The method of one of claims 1 and 2 , wherein at least one control circuit portion sends configuration information about one or more bus or processing circuit portions to an adjacent control circuit portion, wherein the configuration information causes a change of state of the one or more bus or processing circuit portions.
4. The method of one of claims 1 and 2 , wherein at least one control circuit portion sends configuration information about one or more bus or processing circuit portions to another control circuit portion, wherein the configuration information causes a change of state of the one or more bus or processing circuit portions.
5. The method of one of claims 1 and 2 , wherein at least one control circuit portion sends configuration information about one or more bus or processing circuit portions to an adjacent control circuit portion, wherein the configuration information is that the one or more bus or processing circuit portions are defective.
6. The method of one of claims 1 and 2 , wherein at least one control circuit portion sends configuration information about one or more bus or processing circuit portions to another control circuit portion, wherein the configuration information is that the one or more bus or processing circuit portions are defective.
7. The method of one of claims 1 and 2 , wherein at least one control circuit portion enables or disables at least one other control circuit portion.
8. The method of one of claims 1 and 2 , wherein at least one control circuit portion controls the testing of and enables or disables at least one other control circuit portion.
9. The method of one of claims 1 and 2 , wherein at least one control circuit portion causes a change of state of at least one bus or processing circuit portion.
10. The method of one of claims 1 and 2 , wherein at least one control circuit portion controls the testing of at least one bus or processing circuit portion.
11. The method of one of claims 1 and 2 , wherein at least one control circuit portion receives an operational fault signal from at least one bus or processing circuit portion.
12. The method of one of claims 1 and 2 , wherein at least one control circuit portion configures the operation of at least one bus or processing circuit portion.
13. The method of one of claims 1 and 2 , wherein at least one control circuit portion configures the operation of one or more bus and processing circuit portions when signaled by one of a bus or processing circuit portion.
14. The method of one of claims 1 and 2 , wherein at least one control circuit portion configures the interconnections of at least one bus and processing circuit portions.
15. The method of one of claims 1 and 2 , wherein at least one control circuit portion configures the interconnections of one or more bus and processing circuit portions.
16. The method of one of claims 1 and 2 , wherein the control network performs power management of the stacked integrated circuit.
17. The method of one of claims 1 and 2 , wherein the control network performs power management of the stacked integrated circuit by commanding at least one control circuit portion to do at least one of suspending the operation and lowering the processing rate of one or more bus or processing circuit portions.
18. The method of one of claims 1 and 2 , wherein at least one control circuit portion suspends the operation of one or more bus and processing circuit portions.
19. The method of one of claims 1 and 2 , wherein at least one control circuit portion suspends the operation of one or more bus and processing circuit portions when signaled by one of a bus or processing circuit portion.