Low power bias scheme for mobile storage SOC

1. A system, comprising:

a voltage regulator;

an active circuit which supplies a reference signal as an input to the voltage regulator during a higher power mode;

a passive circuit which supplies a second reference signal as the input to the voltage regulator during a lower power mode, wherein the lower power mode consumes less power than the higher power mode, and the lower power mode is off when the higher power mode is on;

an output scaler adjusting an output of the voltage regulator in accordance with power modes including the higher power mode and lower power mode, and a scaled output of the voltage regulator is fed back to the voltage regulator, wherein the scaled output at the lower power mode is lower than the scaled output at the higher power mode; and

a calibration circuit, the calibration circuit is coupled to both the active circuit and the passive circuit, and configured to calibrate during the higher power mode and be turned off during the lower power mode.

2. The system recited in claim 1 , wherein the active circuit is a bandgap circuit.

3. The system recited in claim 1 , wherein the passive circuit is one or more of the following: a voltage divider circuit, and a resistor network.

4. The system recited in claim 1 , further comprising an embedded multimedia controller (eMMC), wherein the eMMC is coupled to the output of the voltage regulator.

5. The system recited in claim 1 , wherein calibrating comprises determining a value for a tunable passive component in the passive circuit.

6. The system recited in claim 5 , wherein the tunable passive component comprises a tunable resistor for a voltage divider.

7. The system recited in claim 5 , wherein the value is set for next time the system is in the lower power mode.

8. The system recited in claim 5 , wherein determining the value includes scaling an output of the voltage regulator and comparing it to the active circuit using a state machine.

9. The system recited in claim 8 , wherein the state machine uses a sequential linear search.

10. The system recited in claim 8 , wherein the state machine uses a binary search.

11. The system recited in claim 8 , wherein the state machine uses a binary search from MSB to LSB.

12. The system recited in claim 1 , wherein the lower power mode is a sleep mode.

13. The system recited in claim 12 , wherein the active circuit is powered down in the sleep mode.

14. The system recited in claim 13 , wherein the calibration circuit is powered down in the sleep mode.

15. A method, comprising:

using a voltage regulator;

using an active circuit which supplies a reference signal as an input to the voltage regulator during a higher power mode;

using a passive circuit which supplies a second reference signal as the input to the voltage regulator during a lower power mode, wherein the lower power mode consumes less power than the higher power mode, and the lower power mode is off when the higher power mode is on;

using an output scaler adjusting an output of the voltage regulator in accordance with power modes including the higher power mode and lower power mode, and a scaled output of the voltage regulator is fed back to the voltage regulator, wherein the scaled output at the lower power mode is lower than the scaled output at the higher power mode; and

using a calibration circuit, the calibration circuit is coupled to both the active circuit and the passive circuit, and configured to calibrate during the higher power mode and be turned off during the lower power mode.

16. The method of claim 15 , wherein the lower power mode is a sleep mode.

17. The method of claim 16 , wherein the active circuit is powered down in the sleep mode.