IP Library › Granted Patent US 9,804,921
Granted Patent B2
US 9,804,921 · App. 14/968,830 · Granted Oct 31, 2017

Nonvolatile memory apparatus and control method of nonvolatile memory apparatus

Inventor: Masato Suto (Osaka, JP)
Assignee: Panasonic Intellectual Property Management Co., Ltd.
G06F11/1048H03M13/05
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Quick Facts
Patent No.
US 9,804,921
App. No.
14/968,830
Granted
Oct 31, 2017
Kind
B2
Abstract

A nonvolatile memory apparatus is provided with a nonvolatile memory including a plurality of blocks each being a recording area of the data and a unit of erasing of the data, and a controller for controlling writing or reading of the data to/from the nonvolatile memory. Each of the blocks includes pages each being a unit of reading of the data. The controller, when data of a first page is read in response to the data read request from the external apparatus, reads data of an other page other than the first page in a block from which the data is read, and calculates a number of errors of the data in the other page, and rewrites the data into an other block when the block from which the data is read satisfies a predetermined condition on the error based on the calculated number of errors.

Claims (18)

1. A nonvolatile memory apparatus for writing or reading data in response to a write or read request of the data from an external apparatus, the nonvolatile memory apparatus comprising:

a nonvolatile memory including a plurality of blocks each being a recording area of the data and a unit of erasing of the data; and

a controller for controlling writing or reading of the data to/from the nonvolatile memory,

wherein each of the blocks includes a plurality of pages each being a unit of reading of the data, and

the controller, when data of a first page is read in response to the data read request from the external apparatus, reads data of an other page other than the first page in a block from which the data is read, and

calculates a number of errors of the data in the other page, and

rewrites the data of the block into the other block when the block from which the data is read satisfies a predetermined condition on the error based on the calculated number of errors.

2. The nonvolatile memory apparatus according to claim 1 , wherein the controller reads at least one page other than the first page being in a same block, as the other page other than the first page.

3. The nonvolatile memory apparatus according to claim 2 , wherein the controller randomly selects the at least one page.

4. The nonvolatile memory apparatus according to claim 1 , wherein the controller reads all pages other than the first page in the same block, as the other page other than the first page.

5. The nonvolatile memory apparatus according to claim 4 , wherein the controller reads the page in order from a head of the block during reading of the all pages other than the first page.

6. The nonvolatile memory apparatus according to claim 4 , wherein the controller reads each of the all pages other than the first page in random order.

7. The nonvolatile memory apparatus according to claim 1 , wherein the predetermined condition is that the calculated number of errors is equal to or greater than a predetermined threshold.

8. A control method of a nonvolatile memory apparatus for writing or reading data in response to a write or read request of the data from an external apparatus, the nonvolatile memory apparatus including a plurality of blocks each being a recording area of the data and a unit of erasing of the data, each of the blocks including a plurality of pages each being a unit of reading of the data, the control method of the nonvolatile memory apparatus comprising:

reading data of a first page in response to the data read request from the external apparatus;

reading data of an other page other than the first page in a block from which the data is read;

calculating a number of errors of the data in the other page; and

rewriting the data of the block into the other block when the block from which the data is read satisfies a predetermined condition on the error based on the calculated number of errors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: SUTO, MASATO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 037602/0121 →
Priority Claims (1)
JP 2014-256386 · Dec 18, 2014 · national
Continuity (1)
Related Publication 20160179613A1 · Jun 23, 2016