Method of forming fine patterns in a semiconductor device and method of manufacturing an electronic device
Methods of forming fine patterns having a width and a pitch in semiconductor devices may be used to form a semiconductor device or electronic device. The fine patterns may be formed by forming sacrificial pillars, which in certain examples may be formed from spacer patterns.
1. A method of manufacturing an electronic device, the method comprising:
providing a semiconductor substrate and an insulating layer on the semiconductor substrate;
forming a plurality of first spacer patterns extending in a first direction on the insulating layer;
forming a first planarized layer on the first spacer patterns;
forming a plurality of line mask patterns extending in a second direction on the first planarized layer, the second direction crossing the first direction;
forming a plurality of sacrificial pillars by patterning the first spacer patterns using the line mask patterns as etch masks;
forming a second planarized layer filling gaps between the sacrificial pillars;
forming a plurality of openings in the second planarized layer by removing some of the sacrificial pillars; and
forming a plurality of holes in the insulating layer by etching the insulating layer using the second planarized layer having the openings as an etch mask.
2. The method of claim 1 , wherein the forming the plurality of openings comprises:
forming a photoresist pattern on the second planarized layer; and
removing some of the sacrificial pillars using the photoresist pattern as an etch mask.
3. The method of claim 1 , wherein the forming the plurality of first spacer patterns comprises:
forming a plurality of first sacrificial patterns extending in the first direction on the insulating layer;
forming a plurality of first spacers on sidewalls of the first sacrificial patterns; and
removing the first sacrificial patterns.
4. The method of claim 3 , wherein the forming the first sacrificial patterns comprises:
forming a first sacrificial layer on the insulating layer;
forming a first photoresist pattern extending in the first direction on the first sacrificial layer;
patterning the first sacrificial layer using the first photoresist pattern as an etch mask; and
removing the first photoresist pattern.
5. The method of claim 3 , wherein the forming the plurality of first spacers comprises:
forming a spacer material layer conformally on the first sacrificial patterns; and
performing an etch-back process on the spacer material layer.
6. The method of claim 1 , wherein the forming the plurality of line mask patterns comprises:
forming a hard mask layer on the first planarized layer;
forming a plurality of second spacer patterns extending in the second direction on the hard mask layer; and
patterning the hard mask layer using the second spacer patterns as etch masks.
7. The method of claim 6 , wherein the forming the plurality of second spacer patterns comprises:
forming a plurality of sacrificial patterns extending in the second direction on the hard mask layer;
forming a plurality of spacers on sidewalls of the sacrificial patterns; and
removing the sacrificial patterns.
8. The method of claim 7 , wherein the forming the plurality of sacrificial patterns comprises:
forming a sacrificial layer on the hard mask layer;
forming a photoresist pattern extending in the second direction on the sacrificial layer;
patterning the sacrificial layer using the photoresist pattern as an etch mask; and
removing the photoresist pattern.
9. The method of claim 7 , wherein the forming the plurality of spacers comprises:
forming a spacer material layer conformally on the sacrificial patterns; and
performing an etch-back process on the spacer material layer.
10. The method of claim 1 , wherein the forming the plurality of sacrificial pillars comprises:
performing an anisotropic etching for the first planarized layer and the first spacer patterns; and
removing the line mask patterns and the first planarized layer.
11. The method of claim 1 , wherein the second direction is substantially perpendicular to the first direction.
12. The method of claim 6 , wherein widths of the first spacer patterns and the second spacer patterns are substantially the same as each other.
13. The method of claim 6 , wherein pitches of the first spacer patterns and the second spacer patterns are substantially the same as each other.
14. The method of claim 1 , further comprising:
forming conductive contacts in the holes; and
providing one or more conductive lines on the substrate, each line connected to one or more of the conductive contacts.
15. A method of manufacturing a semiconductor device, the method comprising:
forming a first hard mask layer on an insulating layer;
forming a plurality of sacrificial pillars on the first hard mask layer, the plurality of sacrificial pillars being spaced apart from each other in a first and a second direction, and the first direction being substantially perpendicular to the second direction;
forming a planarized layer filling gaps between the sacrificial pillars;
forming a plurality of openings in the planarized layer by removing some of the sacrificial pillars so as to expose some portions of the first hard mask layer;
forming a hard mask pattern by patterning the first hard mask layer using the planarized layer having the openings as an etch mask; and
forming a plurality of holes in the insulating layer by etching the insulating layer using the hard mask pattern as an etch mask.
16. The method of claim 15 , wherein the forming the plurality of sacrificial pillars comprises:
forming a plurality of first spacer patterns extending in the first direction on the first hard mask layer;
forming a plurality of line mask patterns extending in the second direction on the first spacer patterns; and
patterning the first spacer patterns using the line mask patterns as etch masks.
17. A method of manufacturing an electronic device, the method comprising:
providing a semiconductor substrate;
providing an insulating layer on the semiconductor substrate;
forming a plurality of first spacer patterns on the substrate, the plurality of first spacer patterns extending in a first direction;
forming a plurality of second spacer patterns on the substrate, the plurality of second spacer patterns extending in a second direction and crossing the plurality of first spacer patterns;
using the second spacer patterns to form spacer mask pillars from the first spacer patterns;
removing some of the spacer mask pillars to form holes in the insulating layer; and
filling the holes with a conductive material.
18. The method of claim 17 , wherein the second spacer patterns are at a vertical height above the first spacer patterns.
19. The method of claim 18 , wherein the conductive material in the holes comprise conductive contacts connected to one or more conductive lines, and further comprising:
providing a plurality of transistors connected to the conductive contacts, the transistors being part of a semiconductor chip; and
forming an electronic device that includes the semiconductor chip.
20. The method of claim 18 , further comprising:
forming the plurality of first spacer patterns by:
forming a first hard mask layer on the insulating layer,
forming a first sacrificial pattern on the first hard mask layer, and
forming the first spacer patterns on sidewalls of the first sacrificial pattern; and
forming the plurality of second spacer patterns by:
forming a first planarization layer on the plurality of first spacer patterns,
forming a second sacrificial pattern on the first planarization layer, and
forming the second spacer patterns on sidewalls of the second sacrificial pattern.