Semiconductor device and method for manufacturing the same
View Patent ↗Objects are to obtain a minute transistor by reducing the channel length L of a transistor used in a semiconductor integrated circuit such as an LSI, a CPU, or a memory, increase the operation speed of the circuit, and reduce power consumption. Oxide layers having compositions different from the composition of an oxide semiconductor layer including a channel formation region are provided below and over the oxide semiconductor layer, and in the oxide semiconductor layer including the channel formation region, low-resistance regions are provided to interpose the channel formation region therebetween in the lateral direction. The low-resistance regions are formed in a region other than the channel formation region so as to be in contact with a metal film or a metal oxide film by diffusion of a metal element (e.g., aluminum) contained in the metal or metal oxide films into the parts of the oxide semiconductor layer.
1. A semiconductor device comprising:
a first oxide layer over a semiconductor substrate;
an oxide semiconductor layer comprising a channel formation region over the first oxide layer;
a second oxide layer over the oxide semiconductor layer and overlapping with the channel formation region;
an insulating layer over the second oxide layer and overlapping with the channel formation region;
a gate electrode layer over the insulating layer; and
a low-resistance region on the oxide semiconductor layer,
wherein a side surface of the first oxide layer and a side surface of the oxide semiconductor layer are substantially aligned with each other,
wherein the second oxide layer is in contact with a top surface and the side surface of the oxide semiconductor layer,
wherein the gate electrode layer surrounds the top surface and the side surface of the oxide semiconductor layer,
wherein the low-resistance region has a lower resistance than the channel formation region,
wherein the channel formation region has a composition different from a composition of the low-resistance region,
wherein the first oxide layer, the oxide semiconductor layer, and the second oxide layer each comprises an oxide comprising In, an element M, and Zn,
wherein the element M is any one of Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, and Hf, and
wherein an atomic ratio of the element M to In in each of the first and second oxide layers is higher than an atomic ratio of the element M to In in the oxide semiconductor layer.
2. The semiconductor device according to claim 1 , further comprising a protective insulating layer over the gate electrode layer and the low-resistance region,
wherein the low-resistance region comprises a first component included in the oxide semiconductor layer and a second component included in the protective insulating layer.
3. The semiconductor device according to claim 1 , wherein the low-resistance region contains aluminum.
4. The semiconductor device according to claim 1 , wherein the low-resistance region is formed in a self-aligned manner utilizing the gate electrode layer.
5. The semiconductor device according to claim 1 , wherein a channel length of the channel formation region is less than or equal to 100 nm.
6. The semiconductor device according to claim 1 , wherein a channel width of the channel formation region is less than or equal to 100 nm.
7. A semiconductor device comprising:
a first protective insulating layer containing aluminum oxide over a semiconductor substrate;
a first oxide layer over the first protective insulating layer;
an oxide semiconductor layer comprising a channel formation region over the first oxide layer;
a second oxide layer over the oxide semiconductor layer and overlapping with the channel formation region;
an insulating layer over the second oxide layer and overlapping with the channel formation region;
a gate electrode layer over the insulating layer;
a low-resistance region on the oxide semiconductor layer; and
a second protective insulating layer containing aluminum oxide over the gate electrode layer and the low-resistance region,
wherein the low-resistance region has a lower resistance than the channel foimation region,
wherein a side surface of the first oxide layer and a side surface of the oxide semiconductor layer are substantially aligned with each other,
wherein the second oxide layer is in contact with a top surface and the side surface of the oxide semiconductor layer,
wherein the gate electrode layer surrounds the top surface and the side surface of the oxide semiconductor layer,
wherein the second protective insulating layer is in contact with a side surface of the low-resistance region and side surfaces of the second oxide layer,
wherein the second protective insulating layer comprises a region in contact with the first protective insulating layer,
wherein the first oxide layer, the oxide semiconductor layer, and the second oxide layer each comprises an oxide comprising In, an element M, and Zn,
wherein the element M is any one of Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, and Hf, and
wherein an atomic ratio of the element M to In in each of the first and second oxide layers is higher than an atomic ratio of the element M to In in the oxide semiconductor layer.
8. The semiconductor device according to claim 7 , wherein the low-resistance region contains aluminum.
9. The semiconductor, device according to claim 7 , wherein the low-resistance region is formed in a self-aligned manner utilizing the gate electrode layer.
10. The semiconductor device according to claim 7 , wherein a channel length of the channel formation region is less than or equal to 100 nm.
11. The semiconductor device according to claim 7 , wherein a channel width of the channel formation region is less than or equal to 100 nm.