Power distribution network (PDN) conditioner
Systems and methods for conditioning a power rail (e.g., reducing voltage droops and/or voltage overshoots on the power rail) are described herein. In one embodiment, a power circuit comprises a capacitor coupled to a high-voltage rail, and a droop slope limiter (DSL) coupled between the high-voltage rail and a power rail. The DSL is configured to detect a downward voltage slope on the power rail, and to control current flow from the high-voltage rail to the power rail through the DSL based on the detected downward voltage slope.
1. A power circuit, comprising:
a capacitor coupled to a high-voltage rail; and
a droop slope limiter (DSL) coupled between the high-voltage rail and a power rail, wherein the DSL comprises:
a slope-detection circuit configured to detect a downward voltage slope on the power rail, and to output a slope signal based on the detected downward voltage slope;
a power transistor coupled between the high-voltage rail and the power rail; and
a control circuit configured to compare the slope signal from the slope-detection circuit with a slope-threshold signal, to turn on the power transistor if the slope signal is above the slope-threshold signal to allow current flow from the capacitor to the power rail, and to turn off the power transistor if the slope signal is below the slope-threshold signal to block the current flow from the capacitor to the power rail.
2. The power circuit of claim 1 , wherein the high-voltage rail is at a voltage that is at least 50 percent greater than the power rail.
3. The power circuit of claim 1 , wherein, during a time that the power transistor is turned on, the control circuit is configured to control the current flow through the power transistor such that a magnitude of the detected downward voltage slope is approximately limited to a slope threshold.
4. The power circuit of claim 1 , wherein the power transistor comprises a field effect transistor (FET), and the control circuit is configured to turn the power transistor on and off by controlling a gate voltage of the power transistor.
5. The power circuit of claim 1 , further comprising an overshoot slope limiter (OSL) coupled between the power rail and a ground, wherein the OSL is configured to detect an upward voltage slope on the power rail, and to control current flow from the power rail to the ground through the OSL based on the detected upward voltage slope.
6. The power circuit of claim 5 , wherein the OSL is configured to control the current flow from the power rail to the ground by blocking the current flow from the power rail to the ground if the detected upward voltage slope is below a slope threshold, and allowing the current flow from the power rail to the ground if the detected upward voltage slope exceeds the slope threshold.
7. The power circuit of claim 6 , wherein, during a time that the OSL allows the current flow from the power rail to the ground, the OSL is configured to control the current flow from the power rail to the ground through the OSL such that the detected upward voltage slope is approximately limited to the slope threshold.
8. The power circuit of claim 1 , wherein the power circuit is integrated on a single chip.
9. The power circuit of claim 8 , further comprising a head switch coupled between the power rail and a circuit on the chip, wherein the head switch is configured to power gate the circuit on the chip.
10. A method for conditioning a power rail, comprising:
detecting a downward voltage slope on the power rail; and
controlling current flow from a capacitor to the power rail via a high-voltage rail based on the detected downward voltage slope, wherein controlling the current flow further comprises:
blocking the current flow from the capacitor to the power rail if a magnitude of the detected downward voltage slope is below a slope threshold; and
allowing the current flow from the capacitor to the power rail if the magnitude of the detected downward voltage slope exceeds the slope threshold.
11. The method of claim 10 , wherein the high-voltage rail is at a voltage that is at least 50 percent greater than the power rail.
12. The method of claim 10 , wherein allowing the current flow further comprises adjusting the current flow such that the magnitude of the detected downward voltage slope is approximately limited to the slope threshold.
13. The method of claim 12 , wherein a field effect transistor (FET) is coupled between the high-voltage rail and the power rail, and adjusting the current flow comprises adjusting a gate voltage of the FET.
14. The method of claim 10 , further comprising:
detecting an upward voltage slope on the power rail; and
controlling current flow from the power rail to a ground based on the detected upward voltage slope.
15. The method of claim 14 , wherein controlling the current flow from the power rail to the ground further comprises:
blocking the current flow from the power rail to the ground if the detected upward voltage slope is below a slope threshold; and
allowing the current flow from the power rail to the ground if the detected upward voltage slope exceeds the slope threshold.
16. The method of claim 15 , wherein allowing the current flow from the power rail to the ground further comprises adjusting the current flow from the power rail to the ground such that the detected upward voltage slope is approximately limited to the slope threshold.
17. The method of claim 10 , wherein the detecting and the controlling are performed on a single chip.
18. An apparatus for conditioning a power rail, comprising:
means for detecting a downward voltage slope on the power rail; and
means for controlling current flow from a capacitor to the power rail via a high-voltage rail based on the detected downward voltage slope, wherein the means for controlling the current flow further comprises:
means for blocking the current flow from the capacitor to the power rail if a magnitude of the detected downward voltage slope is below a slope threshold; and
means for allowing the current flow from the capacitor to the power rail if the magnitude of the detected downward voltage slope exceeds the slope threshold.
19. The apparatus of claim 18 , wherein the high-voltage rail is at a voltage that is at least 50 percent greater than the power rail.
20. The apparatus of claim 18 , wherein the means for allowing the current flow further comprises means for adjusting the current flow such that the magnitude of the detected downward voltage slope is approximately limited to the slope threshold.
21. The apparatus of claim 20 , wherein a field effect transistor (FET) is coupled between the high-voltage rail and the power rail, and the means for adjusting the current flow comprises means for adjusting a gate voltage of the FET.
22. The apparatus of claim 18 , further comprising:
means for detecting an upward voltage slope on the power rail; and
means for controlling current flow from the power rail to a ground based on the detected upward voltage slope.
23. The apparatus of claim 22 , wherein the means for controlling the current flow from the power rail to the ground further comprises:
means for blocking the current flow from the power rail to the ground if the detected upward voltage slope is below a slope threshold; and
means for allowing the current flow from the power rail to the ground if the detected upward voltage slope exceeds the slope threshold.
24. The apparatus of claim 23 , wherein the means for allowing the current flow from the power rail to the ground further comprises means for adjusting the current flow from the power rail to the ground such that the detected upward voltage slope is approximately limited to the slope threshold.
25. The apparatus of claim 18 , wherein the apparatus is integrated on a single chip.
26. The apparatus of claim 25 , further comprising a means for power gating a circuit on the chip, wherein the means for power gating is coupled between the power rail and the circuit on the chip.
27. The power circuit of claim 1 , further comprising a power management integrated circuit (PMIC) connected to the power rail, wherein the PMIC is configured to provide a supply voltage on the power rail when the DSL blocks the current flow from the capacitor to the power rail.
28. The power circuit of claim 27 , wherein the high-voltage rail is at a voltage that is at least 50 percent greater than the supply voltage provided by the PMIC.