Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
1. A method of manufacturing a semiconductor device, comprising:
forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves;
forming a first barrier layer in each groove;
forming an interconnect layer on the first barrier layer to fill each groove;
recessing the interconnect layer and the first barrier layer;
forming a capping pattern on the recessed interconnect layer, the capping pattern being not formed on the first part;
etching at least a portion of the first part by a first etching process;
etching the at least a portion of the first part etched by the first etching process and the capping pattern, by a second etching process to form a trench;
conformally forming a second barrier layer on a sidewall and a bottom surface of the trench and on a top surface of the recessed interconnect layer; and
forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the first part between the grooves.
2. The method according to claim 1 , wherein the first barrier layer includes a conductive material and the second barrier layer includes an insulating material.
3. The method according to claim 1 , wherein the capping pattern includes AlN.
4. The method according to claim 3 , wherein forming the capping pattern comprises:
depositing AlN on the recessed interconnect layer and the first part to form a capping layer including a first portion formed of AlN on the recessed interconnect layer and a second portion formed of AlNO on the first part; and
selectively removing the second portion on the first part to form the capping pattern including AlN on the recessed interconnect layer.
5. The method according to claim 1 , wherein forming the capping pattern comprises forming a first capping pattern and a second capping pattern and a third capping pattern which are sequentially stacked.
6. The method according to claim 5 , wherein the first capping pattern includes Co, the second capping pattern includes CoSiN, and the third capping pattern includes AlN.
7. The method according to claim 6 , wherein forming a first capping pattern and a second capping pattern and a third capping pattern which are sequentially stacked comprises:
depositing Co on the recessed interconnect layer to form the first capping pattern including Co;
performing a silicidation process and a nitrification process on the first capping pattern to form the second capping pattern including CoSiN on the first capping pattern;
depositing AlN on the second capping pattern, the first barrier layer and the first part to form a capping layer including a first portion formed of AlN on the recessed interconnect layer and a second portion formed of AlNO on the first part; and
selectively removing the second portion on the first part to form the third capping pattern including AlN on the recessed interconnect layer.
8. The method according to claim 6 , wherein etching the at least a portion of the first part etched by the first etching process and the capping pattern, by a second etching process comprises removing the second and third capping patterns to leave the first capping pattern on the recessed interconnect layer.
9. The method according to claim 8 , wherein conformally forming a second barrier layer comprises forming the second barrier layer formed on the first capping pattern on the recessed interconnect layer and contacting the first capping pattern.
10. The method according to claim 1 , wherein the first etching process comprises a dry etching process.
11. The method according to claim 1 , wherein the second etching process comprises at least one of an EKC strip process, an NH3 RF plasma process, and a hydro fluoric acid strip process.
12. The method according to claim 1 , wherein the first etching process comprises performing a dry etching process, and
the second etching process comprises:
performing an EKC strip process; and then
performing an NH3 RF plasma process and a hydro fluoric acid strip process.
13. The method according to claim 1 , further comprising:
forming a mask pattern having an opening on the capping pattern and the first part, the opening exposing the at least a portion of the first part and the capping pattern,
wherein etching the first part by a first etching process comprises etching the at least a portion of the first part exposed by the opening, by the first etching process.
14. The method according to claim 1 , further comprises:
forming the trench by the second etching process in a manner such that a width of an upper portion of the trench near the capping pattern is greater than a width of a lower portion of trench near the bottom surface of the interconnect layer.
15. A method of manufacturing a semiconductor device, comprising:
forming grooves in a first dielectric layer on a substrate, the first dielectric layer including an first part between the grooves;
forming a first barrier layer in each groove;
forming an interconnect layer on the first barrier layer to fill each groove;
recessing the interconnect layer and the first barrier layer;
forming a first capping pattern and a second capping pattern on the recessed interconnect layer, the first and second capping patterns being not formed on the first part;
etching at least a portion of the first part by a first etching process;
etching the at least a portion of the first part etched by the first etching process and the second capping pattern, by a second etching process to form a trench;
conformally forming a second barrier layer on a sidewall and a bottom surface of the trench and on the first capping pattern; and
forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the first part between the grooves.
16. The method according to claim 15 , wherein the first capping pattern includes Co and the second capping pattern includes CoSi.
17. The method according to claim 15 , wherein the first capping pattern includes Co and the second capping pattern includes CoSiN.
18. The method according to claim 17 , wherein forming the first capping pattern and the second capping pattern comprises:
depositing Co on the recessed interconnect layer to form the first capping pattern including Co; and
performing a silicidation process and a nitrification process on the first capping pattern to form the second capping pattern including CoSiN on the first capping pattern.
19. The method according to claim 15 , wherein etching the at least a portion of the first part etched by the first etching process and the first capping pattern, by a second etching process comprises removing the second capping pattern to leave the first capping pattern on the recessed interconnect layer, and
wherein conformally forming a second barrier layer comprises forming the second barrier layer formed on the first capping pattern on the recessed interconnect layer and contacting the first capping pattern.
20. A method of manufacturing a semiconductor device, comprising:
forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves;
forming a first barrier layer in each groove;
forming an interconnect layer on the first barrier layer to fill each groove;
recessing the interconnect layer and the first barrier layer;
forming a capping pattern on the recessed interconnect layer, the capping pattern being not formed on the first part;
etching at least a portion of the first part by a first etching process;
etching the at least a portion of the first part etched by the first etching process and the capping pattern, by a second etching process to form a trench;
conformally forming a second barrier layer on a sidewall and a bottom surface of the trench and on a top surface of the recessed interconnect layer; and
forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the first part between the grooves, wherein
forming of the air gap comprises forming the second dielectric layer on the second barrier layer not to fill the trench in a manner such that a bottom surface of the air gap is higher than a bottom surface of each groove.