IP Library Granted Patent US 9,812,491
Granted Patent B2
US 9,812,491 · App. 15/441,308 · Granted Nov 7, 2017

Imaging device

Inventors: Tokuhiko Tamaki (Osaka, JP); Takeyoshi Tokuhara (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L27/14665H01L27/14614H01L27/14627H01L27/14636H04N5/355H04N5/3698
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Quick Facts
Patent No.
US 9,812,491
App. No.
15/441,308
Granted
Nov 7, 2017
Kind
B2
Abstract

An imaging device including: pixel cells each comprising: a photoelectric converter including two electrodes and a photoelectric conversion layer therebetween; a field effect transistor having a gate and a channel region; and a node between the photoelectric converter and the field effect transistor. The field effect transistor outputs an electric signal corresponding to change in dielectric constant between the electrodes, the change being caused by incident light on the photoelectric conversion layer. Cpd 1, Cn 1, Cpd 2 and Cn 2 satisfy a relation of Cpd 1 /Cn 1 <Cpd 2 /Cn 2 where a capacitance value of a first photoelectric converter in a state of receiving no incident light is Cpd 1, a capacitance value between a first node and a first channel region is Cn 1, a capacitance value of a second photoelectric converter in a state of receiving no incident light is Cpd 2, and a capacitance value between a second node and a second channel region is Cn 2.

Claims (32)

1. An imaging device comprising:

a first pixel cell comprising:

a first photoelectric converter including a first electrode, a second electrode facing the first electrode, and a first photoelectric conversion layer between the first electrode and the second electrode;

a first field effect transistor having a first gate and a first channel region, the first gate being connected to the first electrode; and

a first node between the first photoelectric converter and the first field effect transistor, and

a second pixel cell comprising:

a second photoelectric converter including a third electrode, a fourth electrode facing the third electrode, and a second photoelectric conversion layer between the third electrode and the fourth electrode;

a second field effect transistor having a second gate and a second channel region, the second gate being connected to the third electrode, and

a second node between the first photoelectric converter and the second field effect transistor, wherein

the first field effect transistor outputs a first electric signal corresponding to change in dielectric constant between the first electrode and the second electrode, the change being caused by incident light on the first photoelectric conversion layer,

the second field effect transistor outputs a second electric signal corresponding to change in dielectric constant between the third electrode and the fourth electrode, the change being caused by incident light on the second photoelectric conversion layer, and

Cpd 1 , Cn 1 , Cpd 2 and Cn 2 satisfy a relation of Cpd 1 /Cn 1 <Cpd 2 /Cn 2 where a value of capacitance of the first photoelectric converter in a state of receiving no incident light is represented as Cpd 1 , a value of capacitance between the first node and the first channel region is represented as Cn 1 , a value of capacitance of the second photoelectric converter in a state of receiving no incident light is represented as Cpd 2 , and a value of capacitance between the second node and the second channel region is represented as Cn 2 .

2. The imaging device according to claim 1 , wherein the first photoelectric conversion layer and the second photoelectric conversion layer are a single continuous layer.

3. The imaging device according to claim 1 , wherein the second electrode and the fourth electrode are a single continuous electrode.

4. The imaging device according to claim 1 , comprising a plurality of pixel cells including the first pixel cell and the second pixel cell, wherein the plurality of pixel cells are arranged one-dimensionally or two-dimensionally.

5. The imaging device according to claim 1 , wherein the first pixel cell is directly adjacent to the second pixel cell.

6. The imaging device according to claim 1 , wherein

the capacitance between the first node and the first channel region includes a capacitance of a first gate insulating layer of the first field effect transistor, and

the capacitance between the second node and the second channel region includes a capacitance of a second gate insulating layer of the second field effect transistor.

7. The imaging device according to claim 1 , wherein

each of the first photoelectric conversion layer and the second photoelectric conversion layer has a photocurrent characteristic between a bias voltage and an output current density, the photocurrent characteristic including a first voltage range where an absolute value of the output current density increases as the bias voltage increases in a reverse direction, a second voltage range where the output current density increases as the bias voltage increases in a forward direction, and a third voltage range where an absolute value of a change rate of the output current density relative to the bias voltage is smaller than in the first voltage range and the second voltage range, the third voltage range being a voltage range between the first voltage range and the second voltage range.

8. The imaging device according to claim 7 , further comprising

a first voltage supply circuit that supplies a first bias voltage within the third voltage range to the first photoelectric conversion layer, and

a second voltage supply circuit that supplies a second bias voltage within the third voltage range to the second photoelectric conversion layer.

9. The imaging device according to claim 7 , further comprising

a first controller that causes the first voltage supply circuit to supply the first bias voltage, and

a second controller that causes the second voltage supply circuit to supply the second bias voltage.

10. The imaging device according to claim 7 , wherein the first bias voltage is equal to the second bias voltage.

11. The imaging device according to claim 1 , wherein, in a plan view, an area of the first electrode is smaller than an area of the third electrode.

12. The imaging device according to claim 1 , wherein, in a plan view, an area of a gate insulating layer of the first field effect transistor is larger than an area of a gate insulating layer of the second field effect transistor.

13. The imaging device according to claim 1 , wherein a thickness of a gate insulating layer of the first field effect transistor is smaller than a thickness of a gate insulating layer of the second field effect transistor.

14. The imaging device according to claim 1 , wherein the first pixel cell includes a microlens located on the second electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2017
From: TAMAKI, TOKUHIKO; TOKUHARA, TAKEYOSHI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 042087/0382 →
Priority Claims (1)
JP 2016-047452 · Mar 10, 2016 · national
Continuity (1)
Related Publication 20170263669A1 · Sep 14, 2017