IP Library Granted Patent US 9,816,187
Granted Patent B2
US 9,816,187 · App. 15/278,455 · Granted Nov 14, 2017

PECVD process

Inventors: Nagarajan Rajagopalan (Santa Clara, CA); Xinhai Han (Santa Clara, CA); Michael Wenyoung Tsiang (Fremont, CA); Masaki Ogata (San Jose, CA); Zhijun Jiang (Sunnyvale, CA); Juan Carlos Rocha-Alvarez (San Carlos, CA); Thomas Nowak (Cupertino, CA); Jianhua Zhou (Campbell, CA); Ramprakash Sankarakrishnan (Santa Clara, CA); Amit Kumar Bansal (Milpitas, CA); Jeongmin Lee (Sunnyvale, CA); Todd Egan (Fremont, CA); Edward Budiarto (Fremont, CA); Dmitriy Panasyuk (Santa Clara, CA); Terrance Y. Lee (Oakland, CA); Jian J. Chen (Fremont, CA); Mohamad A. Ayoub (Los Gatos, CA); Heung Lak Park (San Jose, CA); Patrick Reilly (Dublin, CA); Shahid Shaikh (Santa Clara, CA); Bok Hoen Kim (San Jose, CA); Sergey Starik (Kiev, UA); Ganesh Balasubramanian (Sunnyvale, CA)
Assignee: APPLIED MATERIALS, INC.
C23C16/52C23C16/458C23C16/4557C23C16/45565C23C16/46C23C16/50C23C16/505C23C16/509C23C16/5096G01B11/0625G01B11/0683G01N21/55G01N21/658H01L21/00H01L21/67248H01L21/67253H01L21/687G01N2201/1222
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,816,187
App. No.
15/278,455
Granted
Nov 14, 2017
Kind
B2
Abstract

A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

Claims (37)

1. A semiconductor processing apparatus, comprising:

a chamber with a side wall and a floor;

a lid coupled to the side wall, and together with the side wall and floor defining an internal volume, the lid comprising:

a gas distributor having a plurality of gas flow openings; and

a metrology device that directs and receives light through one of the gas flow openings; and

a substrate support disposed in the internal volume.

2. The apparatus of claim 1 , wherein the metrology device directs light toward the substrate support and receives light reflected from inside the internal volume.

3. The apparatus of claim 1 , wherein the lid further comprises a zoned plate having a gas flow opening aligned with a gas flow opening of the gas distributor, wherein the metrology device directs and receives light through the gas flow openings of the zoned plate and the gas distributor.

4. The apparatus of claim 3 , wherein the lid further comprises a second zoned plate and the metrology device includes a collimator that fits an opening in the second zoned plate.

5. The apparatus of claim 4 , wherein the collimator does not contact the second zoned plate when disposed in the opening of the second zoned plate.

6. The apparatus of claim 3 , further comprising an electrode between the gas distributor and the side wall.

7. The apparatus of claim 6 , wherein the electrode is coupled to a tuning circuit having a variable impedance.

8. The apparatus of claim 7 , wherein the tuning circuit comprises a variable capacitor.

9. The apparatus of claim 6 , wherein the lid further comprises a heater.

10. The apparatus of claim 9 , wherein the heater is disposed at a periphery of the gas distributor.

11. The apparatus of claim 10 , wherein the substrate support comprises a zoned heater.

12. A semiconductor processing apparatus, comprising:

a chamber with a side wall and a floor;

a lid coupled to the side wall, and together with the side wall and floor defining an internal volume, the lid comprising:

a gas distributor having a plurality of gas flow openings; and

a metrology device that directs and receives light through one of the gas flow openings;

a substrate support disposed in the internal volume; and

an electrode between the gas distributor and the side wall.

13. The apparatus of claim 12 , wherein the metrology device comprises a fiber optic and a collimator housing the fiber optic, and the collimator fits an opening formed in the lid.

14. The apparatus of claim 13 , wherein the lid comprises a first zoned plate and a second zoned plate, and the opening is formed in the second zoned plate.

15. The apparatus of claim 14 , wherein the collimator seats in the first zoned plate.

16. The apparatus of claim 15 , wherein the collimator does not contact the second zoned plate when disposed in the opening of the second zoned plate.

17. The apparatus of claim 16 , wherein the substrate support comprises a zoned heater.

18. The apparatus of claim 17 , wherein the electrode is coupled to a variable impedance source.

19. A semiconductor processing apparatus, comprising:

a chamber with a side wall and a floor;

a lid coupled to the side wall, and together with the side wall and floor defining an internal volume, the lid comprising:

a gas distributor having a plurality of gas flow openings; and

a metrology device that directs and receives light through one of the gas flow openings;

a substrate support disposed in the internal volume; and

an electrode between the gas distributor and the side wall, the electrode coupled to a variable impedance source.

20. The apparatus of claim 19 , wherein the lid comprises a first zoned plate and a second zoned plate, an opening is formed in the second zoned plate, the metrology device comprises a fiber optic and a collimator housing the fiber optic, and the collimator fits the opening in the second zoned plate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2016
From: RAJAGOPALAN, NAGARAJAN; HAN, XINHAI; TSIANG, MICHAEL WENYOUNG; OGATA, MASAKI; JIANG, ZHIJUN; ROCHA-ALVAREZ, JUAN CARLOS; NOWAK, THOMAS; ZHOU, JIANHUA; SANKARAKRISHNAN, RAMPRAKASH; BANSAL, AMIT KUMAR; LEE, JEONGMIN; EGAN, TODD; BUDIARTO, EDWARD; PANASYUK, DMITRIY; LEE, TERRANCE Y.; CHEN, JIAN J.; AYOUB, MOHAMAD A.; PARK, HEUNG LAK; REILLY, PATRICK; SHAIKH, SHAHID; KIM, BOK HOEN; STARIK, SERGEY; BALASUBRAMANIAN, GANESH
To: APPLIED MATERIALS, INC.
Reel/Frame 040170/0895 →
Continuity (6)
Continuation 14869371 · Sep 29, 2015
Continuation 14056203 · Oct 17, 2013
Provisional Application 61761515 · Feb 6, 2013
Provisional Application 61738247 · Dec 17, 2012
Provisional Application 61719319 · Oct 26, 2012
Related Publication 20170016118A1 · Jan 19, 2017