Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs

1. A computer implemented method for implementing additional connectivity for an electronic design, comprising:

using at least one processor or at least one processor core to perform a process the process comprising:

identifying one or more regions for a route in normal connectivity that is accessible by a connectivity iterator module that iterates over a first plurality of geometric entities for an electronic design;

identifying a plurality of seeding segments from the route based at least in part upon the one or more regions;

generating, at a different connectivity iterator module, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and

implementing a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator module from the physical design based at least in part upon the plurality of additional nodes.

2. The computer implemented method of claim 1 , further comprising:

identifying the plurality of additional nodes in the plurality of seeding segments; and

incorporating the plurality of additional nodes and the one or more additional routes into additional connectivity that is different from the normal connectivity.

3. The computer implemented method of claim 1 , wherein the act of generating the one or more additional routes is performed without disturbing the normal connectivity that includes a plurality of Steiner points and the route.

4. The computer implemented method of claim 1 , the process further comprising:

identifying one or more design rules, wherein

the act of identifying the one or more regions is performed based at least in part upon the one or more design rules, and

the one or more seeding segments are determined by subtracting the one or more regions from a first geometric entity including the route.

5. The computer implemented method of claim 1 , the process further comprising:

searching for connectivity for a viable routing solution using a search probe or a search strategy when the search probe or the search strategy encounters a first additional node of the plurality of additional nodes instead of looking up the connectivity in a data structure, wherein

the connectivity for the viable routing solution does not alter the normal connectivity including the route.

6. The computer implemented method of claim 5 , further comprising:

determining a final location of a first additional node of the plurality of additional nodes based at least in part upon results of searching for the connectivity.

7. The computer implemented method of claim 5 , further comprising:

identifying a normal connectivity iterator for manipulating the normal connectivity; and

identifying an additional connectivity iterator for manipulating the additional connectivity, wherein

the normal connectivity iterator maintains the normal connectivity and ignores or does not have access to the additional connectivity,

the additional connectivity iterator maintains the additional connectivity and is allowed to access both the normal connectivity and the additional connectivity, and

the act of searching for the connectivity is performed by using at least the additional connectivity iterator.

8. The computer implemented method of claim 1 , the process further comprising:

designating the one or more regions as keep-out area to remove the one or more regions from routing resource that is used to implement the one or more additional routes.

9. The computer implemented method of claim 1 , the process further comprising:

determining whether or not wrong-way routing is permitted in at least a portion of the electronic design including the plurality of additional routes;

determining whether or not spacetiles are used to implement at least one of the plurality of additional routes; and

determining a route type for the plurality of additional routes, wherein the route is not of the new route type.

10. The computer implemented method of claim 1 , the process further comprising:

determining whether at least one additional node of the plurality of the one or more additional nodes is to be removed based at least in part upon one or more rules, wherein

the at least one additional node is to be removed by an additional connectivity iterator associated with the additional connectivity but not by a normal connectivity iterator associated with the normal connectivity, and

determining whether an additional node of the plurality of the one or more additional nodes is redundant by using the additional connectivity iterator and not by using the normal connectivity iterator.

11. The computer implemented method of claim 1 , the processing further comprising:

determining whether a Steiner point is allowed in the additional connectivity; and

adding a first route connecting to the Steiner point to the additional connectivity when the Steiner point is determined to be allowed in the additional connectivity.

12. The computer implemented method of claim 1 , the process further comprising at least one of:

labeling some but not all of additional routes in the additional connectivity;

adding a purpose for the additional connectivity;

grouping the additional connectivity into a selection set for one or more additional operations; and

verifying a net in the electronic design by using a search strategy while ignoring the additional connectivity.

13. The computer implemented method of claim 1 , the process further comprising at least one of:

determining whether one or more additional nodes of the plurality of additional nodes for the additional connectivity are redundant in the electronic design based at least in part upon the route;

generating and using a first class of objects for the additional connectivity to guide one or more electronic design automation tools; and

generating and using a second class of objects for temporarily blocking the one or more regions to implement the additional connectivity.

14. The computer implemented method of claim 1 , the process further comprising:

identifying a global or conduit route in the electronic design;

identifying one or more global additional nodes for the global or conduit route; and

updating the additional connectivity to incorporate the one or more global additional nodes.

15. The computer implemented method of claim 14 , the process further comprising:

associating the one or more global additional nodes with the normal connectivity and / or one or more circuit components connected via the normal connectivity; and

implementing the global or conduit route by using the one or more global additional nodes.

16. A system for implementing additional connectivity for an electronic design, comprising:

at least one processor or at least one processor core that is at least to:

identify one or more regions for a route in normal connectivity that is accessible by a connectivity iterator that iterates over a first plurality of geometric entities for an electronic design;

identify a plurality of seeding segments from the route based at least in part upon the one or more regions;

generate, at a different connectivity iterator, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and

implement a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator from the physical design based at least in part upon the plurality of additional nodes.

17. The system of claim 16 , wherein the at least one processor or at least one processor core is further to:

search for connectivity for a viable routing solution using a search probe or a search strategy when the search probe or the search strategy encounters a first additional node of the plurality of additional nodes instead of looking up the connectivity in a data structure, wherein

the connectivity for the viable routing solution does not alter the normal connectivity including the route, and

the at least one processor or at least one processor core generates the one or more additional routes without disturbing the normal connectivity that includes a plurality of Steiner points and the route.

18. The system of claim 17 , wherein the at least one processor or at least one processor core is further to:

determine a final location of a first additional node of the plurality of additional nodes based at least in part upon results of searching for the connectivity; and

identify a normal connectivity iterator for manipulating the normal connectivity;

identify an additional connectivity iterator for manipulating the additional connectivity, wherein

the normal connectivity iterator maintains the normal connectivity and ignores or does not have access to the additional connectivity.

19. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a process for implementing additional connectivity for an electronic design, the process comprising:

identifying one or more regions for a route in normal connectivity that is accessible by a connectivity iterator module that iterates over a first plurality of geometric entities for an electronic design;

identifying a plurality of seeding segments from the route based at least in part upon the one or more regions;

generating, at a different connectivity iterator module, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and

implementing a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator module from the physical design based at least in part upon the plurality of additional nodes.

20. The article of manufacture of claim 19 , the process further comprising:

searching for connectivity for a viable routing solution using a search probe or a search strategy when the search probe or the search strategy encounters a first additional node of the plurality of additional nodes instead of looking up the connectivity in a data structure, wherein

the connectivity for the viable routing solution does not alter the normal connectivity including the route; and

the act of generating the one or more additional routes is performed without disturbing the normal connectivity that includes a plurality of Steiner points and the route.