Scan driver ADN display device using the same

1. A display device, comprising:

a display panel having a display area and a non-display area outside the display area;

a data driver that supplies a data signal to the display panel; and

a scan driver in the non-display area that includes a shift register of a plurality of stages and a level shifter, and that supplies a scan signal to the display panel using the shift register and the level shifter,

wherein the shift register is arranged in an output terminal of an N-th stage circuit in a first non-display area and an output terminal of an N-th compensation circuit in a second non-display area that is in an opposite side of the first non-display area with the display area therebetween are paired and connected to an N-th scan line,

wherein the N-th stage circuit outputs a first scan signal to the N-th scan line, and the N-th compensation circuit outputs a compensation signal to the N-th scan line in response to a node voltage of a stage circuit that outputs a second scan signal different from the first scan signal.

2. The display device of claim 1 , wherein the N-th compensation circuit outputs the compensation signal to the N-th scan line in response to a voltage of a Q node of a stage circuit immediately adjacent thereto in a vertical direction.

3. The display device of claim 1 , wherein the N-th compensation circuit outputs the compensation signal to the N-th scan line in response to voltages of Q nodes of a stage circuit in a stage prior thereto and a stage circuit in a stage before the prior stage or a stage circuit in a stage following the N-th compensation circuit and a stage circuit in a stage following the following stage.

4. The display device of claim 2 , wherein the N-th compensation circuit outputs a clock signal as the compensation signal.

5. The display device of claim 1 , wherein the N-th compensation circuit includes a compensation transistor having a gate electrode connected to a Q node of a stage circuit immediately adjacent thereto in a vertical direction, a first electrode connected to an N-th clock signal line, and a second electrode connected to the N-th scan line.

6. A scan driver, comprising:

a level shifter; and

a shift register composed of a plurality of stages to generate a scan signal on the basis of a signal and power output from the level shifter,

wherein the shift register includes an N-th stage circuit unit and an N-th compensation circuit unit located on the same line as the N-th stage circuit unit, the N-th stage circuit unit and the N-th compensation circuit unit being arranged to have asymmetrical circuit configurations,

wherein an output terminal of the N-th stage circuit unit and an output terminal of the N-th compensation circuit unit are paired to be connected to an N-th scan line,

wherein the N-th stage circuit outputs a first scan signal to the N-th scan line, and the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a stage circuit unit that outputs a second scan signal different from the first scan signal.

7. The scan driver of claim 6 , wherein the N-th compensation circuit unit outputs the compensation signal to the N-th scan line in response to a voltage of a Q node of a stage circuit unit adjacent thereto in the vertical direction.

8. The scan driver of claim 6 , wherein the N-th compensation circuit unit outputs the compensation signal to the N-th scan line in response to voltages of Q nodes of a stage circuit unit in a stage prior thereto and a stage circuit unit in a stage before the prior stage or a stage circuit unit in a stage following the N-th compensation circuit unit and a stage circuit unit in a stage following the following stage.

9. The scan driver of claim 7 , wherein the N-th compensation circuit outputs a clock signal as the compensation signal.

10. The scan driver of claim 6 , wherein the N-th compensation circuit includes a compensation transistor having a gate electrode connected to a Q node of a stage circuit unit adjacent thereto in the vertical direction, a first electrode connected to an N-th clock signal line, and a second electrode connected to the N-th scan line.

11. A display device, comprising:

a display panel;

a data driver configured to supply a data signal to the display panel; and

a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter,

wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line,

wherein the N-th compensation circuit unit maintains the N-th scan line at a scan low voltage in response to a clock signal having a logic state opposite an N-th clock signal output through the output terminal of the N-th stage circuit unit.

12. The display device of claim 11 , wherein the N-th compensation circuit unit maintains the N-th scan line at the scan low voltage corresponding to a low-level voltage output through the output terminal of the N-th stage circuit unit.

13. The display device of claim 11 , wherein the N-th compensation circuit unit includes: a first compensation transistor having a gate electrode connected to a Q node of an (N+2)-th stage circuit unit, a first electrode connected to an (N+1)-th clock signal line, and a second electrode connected to the N-th scan line; and a second compensation transistor having a gate electrode connected to a clock signal line having a logic state opposite the N-th clock signal, a first electrode connected to a first or second low-level power line, and a second electrode connected to the N-th scan line.

14. A scan driver, comprising:

a level shifter; and

a shift register composed of a plurality of stages to generate a scan signal on the basis of a signal and power output from the level shifter,

wherein the shift register includes an N-th stage circuit unit and an N-th compensation circuit unit located on the same line as the N-th stage circuit unit, the N-th stage circuit unit and the N-th compensation circuit unit being arranged to have asymmetrical circuit configurations,

wherein an output terminal of the N-th stage circuit unit and an output terminal of the N-th compensation circuit unit are paired to be connected to an N-th scan line,

wherein the N-th compensation circuit unit maintains the N-th scan line at a scan low voltage in response to a clock signal having a logic state opposite an N-th clock signal output through the output terminal of the N-th stage circuit unit.

15. The scan driver of claim 14 , wherein the N-th compensation circuit unit maintains the N-th scan line at the scan low voltage corresponding to a low-level voltage output through the output terminal of the N-th stage circuit unit.

16. The scan driver of claim 14 , wherein the N-th compensation circuit unit includes: a first compensation transistor having a gate electrode connected to a Q node of an (N+2)-th stage circuit unit, a first electrode connected to an (N+1)-th clock signal line, and a second electrode connected to the N-th scan line; and a second compensation transistor having a gate electrode connected to a clock signal line having a logic state opposite the N-th clock signal, a first electrode connected to a first or second low-level power line, and a second electrode connected to the N-th scan line.