IP Library Granted Patent US 9,818,681
Granted Patent B2
US 9,818,681 · App. 14/969,555 · Granted Nov 14, 2017

Wiring substrate

Inventor: Yoshihiro Machida (Nagano, JP)
Assignee: Shinko Electric Industries Co., Ltd.
H01L23/49827H01L21/4853H01L23/49811H01L23/49822H01L23/49833H01L24/06H01L24/32H01L24/33H01L24/73H01L24/81H01L24/83H05K1/185H05K3/4614H01L23/49816H01L23/49838H01L24/05H01L24/13H01L24/16H01L24/29H01L2224/0401H01L2224/04026H01L2224/05155H01L2224/05166H01L2224/05644H01L2224/05647H01L2224/06183H01L2224/131H01L2224/13111H01L2224/16014H01L2224/16105H01L2224/16106H01L2224/16175H01L2224/291H01L2224/2919H01L2224/29111H01L2224/32014H01L2224/32105H01L2224/32106H01L2224/32175H01L2224/32227H01L2224/33183H01L2224/73253H01L2224/81424H01L2224/81444H01L2224/81447H01L2224/81815H01L2224/83101H01L2224/83424H01L2224/83444H01L2224/83447H01L2224/83815H01L2924/15311H05K2201/10303H05K2203/061
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Quick Facts
Patent No.
US 9,818,681
App. No.
14/969,555
Granted
Nov 14, 2017
Kind
B2
Abstract

A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an uppermost wiring layer of the first substrate. A connection terminal is formed on the electronic component and is located proximate to the first pad in a plan view. The wiring substrate further includes a connection member formed on the first pad to electrically connect the first pad and the connection terminal. The connection member includes a rod-shaped core and a solder layer, which is coated around the core and joined to the first pad. The solder layer includes a bulge that spreads from the core of the connection member in a planar direction. The bulge is joined to the connection terminal of the electronic component.

Claims (57)

1. A wiring substrate comprising:

a first substrate including an uppermost wiring layer;

a first pad formed on the uppermost wiring layer of the first substrate;

a second substrate mounted above the first substrate and including a lowermost wiring layer;

a second pad formed on the lowermost wiring layer of the second substrate and located at a position facing the first pad of the first substrate;

an electronic component mounted on an upper surface of the first substrate and located between the first substrate and the second substrate;

a connection terminal formed on the electronic component and located proximate to the first pad in a plan view; and

a connection member joined to the first pad, the second pad, and the connection terminal to electrically connect the first pad, the second pad, and the connection terminal,

wherein the connection member includes

a rod-shaped core, and

a solder layer coated around the core and joined to the first pad and the second pad, and

the solder layer includes a bulge that spreads from the core of the connection member in a planar direction, the bulge being joined to the connection terminal of the electronic component.

2. The wiring substrate according to claim 1 , wherein

the solder layer includes a straight rod portion which coats an upper half of the core, and

the bulge of the solder layer is continuous with the straight rod portion and coats a lower half of the core.

3. The wiring substrate according to claim 1 , wherein

the electronic component comprises a chip component that includes a body and two electrode terminals, which cover opposing side surfaces of the body, and

each of the electrode terminals of the chip component functions as the connection terminal.

4. The wiring substrate according to claim 1 , wherein

the electronic component comprises a semiconductor chip that includes a semiconductor substrate having a circuit formation surface and an electrode terminal arranged on the circuit formation surface of the semiconductor substrate,

the semiconductor chip is mounted on the first substrate with a surface opposite to the circuit formation surface faced toward the first substrate, and

the electrode terminal of the semiconductor chip functions as the connection terminal.

5. The wiring substrate according to claim 1 , wherein

the electronic component includes a semiconductor chip that includes a semiconductor substrate having a circuit formation surface and an electrode terminal arranged on the circuit formation surface of the semiconductor substrate,

the semiconductor chip is mounted on the first substrate with the circuit formation surface faced toward the first substrate, and

the electrode terminal of the semiconductor chip functions as the connection terminal.

6. A wiring substrate comprising:

a first substrate including an uppermost wiring layer;

a first pad formed on the uppermost wiring layer of the first substrate;

an electronic component mounted on an upper surface of the first substrate;

a connection terminal formed on the electronic component and located proximate to the first pad in a plan view; and

a connection member formed on the first pad to electrically connect the first pad and the connection terminal, wherein

the connection member includes a rod-shaped core, and

a solder layer coated around the core and joined to the first pad;

the solder layer includes a bulge that spreads from the core of the connection member in a planar direction, the bulge being joined to the connection terminal of the electronic component;

the electronic component comprises a semiconductor chip that includes a semiconductor substrate having a circuit formation surface and an electrode terminal arranged on the circuit formation surface of the semiconductor substrate;

the semiconductor chip is mounted on the first substrate with a surface opposite to the circuit formation surface faced toward the first substrate; and

the electrode terminal of the semiconductor chip functions as the connection terminal.

7. The wiring substrate according to claim 6 , wherein

the solder layer includes a straight rod portion which coats an upper half of the core, and

the bulge of the solder layer is continuous with the straight rod portion and coats a lower half of the core.

8. A wiring substrate comprising:

a first substrate including an uppermost wiring layer;

a first pad formed on the uppermost wiring layer of the first substrate;

an electronic component mounted on an upper surface of the first substrate;

a connection terminal formed on the electronic component and located proximate to the first pad in a plan view; and

a connection member formed on the first pad to electrically connect the first pad and the connection terminal, wherein:

the connection member includes

a rod-shaped core, and

a solder layer coated around the core and joined to the first pad;

the solder layer includes a bulge that spreads from the core of the connection member in a planar direction, the bulge being joined to the connection terminal of the electronic component;

the electronic component includes a semiconductor chip that includes a semiconductor substrate having a circuit formation surface and an electrode terminal arranged on the circuit formation surface of the semiconductor substrate;

the semiconductor chip is mounted on the first substrate with the circuit formation surface faced toward the first substrate; and

the electrode terminal of the semiconductor chip functions as the connection terminal.

9. The wiring substrate according to claim 8 , wherein

the solder layer includes a straight rod portion which coats an upper half of the core, and

the bulge of the solder layer is continuous with the straight rod portion and coats a lower half of the core.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2016
From: MACHIDA, YOSHIHIRO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 037401/0828 →
Priority Claims (1)
JP 2014-263381 · Dec 25, 2014 · national
Continuity (1)
Related Publication 20160190053A1 · Jun 30, 2016