Method for fabricating semiconductor device
A method for fabricating a semiconductor device includes: forming an inter-layer dielectric layer and a sacrificial layer over a substrate so that the sacrificial layer covers the inter-layer dielectric layer; forming a conductive pattern that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer; protruding a first portion of the conductive pattern by removing the sacrificial layer while maintaining a second portion of the conductive pattern inside the inter-layer dielectric layer; oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern; removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern; and forming a variable resistance element on top of the conductive pattern to couple a bottom of the variable resistance element with the top of the second portion of the conductive pattern.
1. A method for fabricating a semiconductor device, comprising:
forming an inter-layer dielectric layer and a sacrificial layer over a substrate so that the sacrificial layer covers the inter-layer dielectric layer;
forming a conductive pattern that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer;
protruding a first portion of the conductive pattern by removing the sacrificial layer while maintaining a second portion of the conductive pattern inside the inter-layer dielectric layer;
oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern;
removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern; and
forming a variable resistance element on top of the conductive pattern to couple a bottom of the variable resistance element with the top of the second portion of the conductive pattern.
2. The method of claim 1 , wherein the forming of the conductive pattern includes:
forming an opening by selectively etching the inter-layer dielectric layer and the sacrificial layer;
forming a conductive material in a thickness that the opening is sufficiently filled; and
polishing the conductive material until the sacrificial layer is exposed.
3. The method of claim 2 , wherein the sacrificial layer has substantially the same polishing rate as the conductive material.
4. The method of claim 2 , wherein the conductive material includes a metal, and the sacrificial layer includes a nitride of the metal.
5. The method of claim 1 , wherein the sacrificial layer has a different etch rate from the conductive pattern and the inter-layer dielectric layer.
6. The method of claim 1 , wherein a width of a lower surface of the variable resistance element is longer than a width of an upper surface of the second portion of the conductive pattern.
7. The method of claim 1 , wherein the variable resistance element includes:
a free layer having a variable magnetization direction,
a pinned layer having a fixed magnetization direction, and
a tunnel barrier layer interposed between the free layer and the pinned layer.
8. The method of claim 1 , wherein the second portion of the conductive pattern and the inter-layer dielectric layer have planarized upper surfaces.
9. The method of claim 1 , wherein the oxidizing of the protruded first portion of the conductive pattern is performed concurrently with the process of removing the sacrificial layer through natural oxidation.
10. A method for fabricating a semiconductor device, comprising:
forming an inter-layer dielectric layer over a substrate;
forming a sacrificial layer over the inter-layer dielectric layer;
forming a primary bottom electrode that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer;
protruding a portion of the primary bottom electrode by removing the sacrificial layer;
oxidizing the protruded portion of the primary bottom electrode;
forming a bottom electrode of a variable resistance element by removing the oxidized portion of the primary bottom electrode; and
forming the other constituent elements of the variable resistance element that is coupled with the bottom electrode over the bottom electrode.
11. The method of claim 10 , wherein the forming of the primary bottom electrode includes:
forming an opening by selectively etching the inter-layer dielectric layer and the sacrificial layer;
forming a conductive material in a thickness that the opening is sufficiently filled; and
polishing the conductive material until the sacrificial layer is exposed.
12. The method of claim 11 , wherein the sacrificial layer has substantially the same polishing rate as the conductive material.
13. The method of claim 11 , wherein the conductive material includes a metal, and the sacrificial layer includes a nitride of the metal.
14. The method of claim 10 , wherein the sacrificial layer has a different etch rate from the primary bottom electrode and the inter-layer dielectric layer.
15. The method of claim 10 , wherein a width of a lower surface of the other constituent elements of the variable resistance element is longer than a width of an upper surface of the bottom electrode.
16. The method of claim 10 , wherein the other constituent elements of the variable resistance element include:
a free layer having a variable magnetization direction,
a pinned layer having a fixed magnetization direction, and
a tunnel barrier layer interposed between the free layer and the pinned layer.
17. The method of claim 10 , wherein the bottom electrode and the inter-layer dielectric layer have planarized upper surfaces.
18. The method of claim 10 , wherein the oxidizing of the protruded portion of the primary bottom electrode is performed concurrently with the process of removing the sacrificial layer through natural oxidation.