Low capacitance transient voltage suppressor
A low capacitance transient voltage suppressor is disclosed. The transient voltage suppressor comprises a first diode with a first anode thereof coupled to an I/O port. A first cathode of the first diode and a second cathode of a second diode are respectively coupled to two ends of a resistor. A second anode of the second diode is coupled to a low-voltage terminal. A third anode and a third cathode of a third diode are respectively coupled to the second cathode and the resistor. The third diode induces a third parasitic capacitance smaller than a first capacitance of the first diode and a second parasitic capacitance of the second diode, and the third parasitic capacitance in series with the first and second parasitic capacitances dominate a small capacitance in a path during normal operation.
1. A low capacitance transient voltage suppressor, comprising:
a first diode having an anode coupled to an I/O port, wherein said first diode induces a first parasitic capacitance;
a resistor having a first terminal coupled to a cathode of said first diode, and a second terminal coupled to a common node;
a second diode having a cathode coupled to said common node, and an anode coupled to a low-voltage terminal, wherein said second diode induces a second parasitic capacitance, and said first and second diodes are turned on to discharge an electrostatic discharge (ESD) transient voltage through said resistor during ESD stressing; and
a third diode having an anode coupled to said common node and a cathode coupled to said resistor, wherein said anode of said third diode comprises a ring structure that laterally surrounds and is separated by a gap from said anode of said first diode, and wherein said third diode induces a third parasitic capacitance that is smaller than said first and second parasitic capacitances, and said third parasitic capacitance in series with said first and second parasitic capacitances dominates a small capacitance in a path during normal operation.
2. The transient voltage suppressor of claim 1 , wherein said second diode comprises a P-type substrate and a first N-type layer thereon, and a second N-type layer on said first N-type layer, wherein said resistor is within said second N-type layer, and said P-type substrate is coupled to said low-voltage terminal.
3. The transient voltage suppressor of claim 2 , wherein said first diode comprises a PN junction between said second N-type layer and a first P-type heavily-doped area, and wherein said third diode comprises a PN junction between said second N-type layer and at least one second P-type heavily-doped area, wherein said first P-type heavily-doped area coupled to said I/O port and said second P-type heavily-doped area coupled to said first N-type layer are formed in said second N-type layer.
4. The transient voltage suppressor of claim 2 , wherein said first diode comprises a PN junction between said second N-type layer and a P-type heavily-doped area, and said third diode comprises a metal-semiconductor (MS) junction between said second N-type layer and at least one thin metal line, wherein said P-type heavily-doped area coupled to said I/O port is formed in said second N-type layer, and said thin metal line coupled to said first N-type layer is formed on said second N-type layer.
5. The transient voltage suppressor of claim 4 , wherein said thin metal line comprises at least one of: titanium (Ti) and silicide metal.
6. The transient voltage suppressor of claim 4 , wherein said thin metal line comprises tungsten (W).
7. The transient voltage suppressor of claim 1 , wherein said second diode comprises a Zener diode.
8. The transient voltage suppressor of claim 1 , wherein said common node comprises a high-voltage terminal.
9. The transient voltage suppressor of claim 1 , wherein said low-voltage terminal is grounded.
10. The transient voltage suppressor of claim 1 , wherein said ring structure is circular.
11. The transient voltage suppressor of claim 1 , wherein each of said first, second, and third-diodes comprises a PN junction.
12. The transient voltage suppressor of claim 1 , wherein said first diode comprises a PN junction, and said third diode comprises a metal-semiconductor (MS) junction.
13. The transient voltage suppressor of claim 3 , wherein said second P-type heavily-doped area at least partially surrounds said first P-type heavily-doped area.
14. The transient voltage suppressor of claim 3 , said second P-type heavily-doped area is smaller than said second N-type layer.
15. The transient voltage suppressor of claim 3 , wherein said second P-type heavily-doped area comprises a ring structure.
16. The transient voltage suppressor of claim 2 , wherein said second P-type heavily-doped area is annually arranged at a side of said first P-type heavily-doped area.
17. The transient voltage suppressor of claim 1 , wherein said third diode comprises first and second PN junctions coupled in parallel.
18. The transient voltage suppressor of claim 17 , wherein said first diode is disposed between said first and second PN junctions.
19. The transient voltage suppressor of claim 1 , wherein said third diode comprises first and second MS junctions coupled in parallel.
20. The transient voltage suppressor of claim 19 , wherein said first diode is disposed between said first and second MS junctions.